AK4128A Datasheet, PDF (40/50 Pages) Asahi Kasei Microsystems – 8ch 216kHz / 24-Bit Asynchronous SRC

[AK4128A]
2. WRITE Operations
Set R/W bit = “0” for the WRITE operation of the AK4128A.
After receipt of a start condition and the first byte, the AK4128A generates an acknowledge, and awaits the second byte
(register address). The second byte consists of the address for control registers of AK4128A. The format is MSB first, and
first 6bits must be fixed to “0”.
0
0
0
0
0
0
A1
A0
(*: Don’t care)
Figure 43. The Second Byte
After receipt the second byte, the AK4128A generates an acknowledge, and awaits the third byte. Those data after the
second byte contain control data. The format is MSB first, 8bits.
D7
D6
D5
D4
D3
D2
D1
D0
Figure 44. Byte structure after the second byte
The AK4128A is capable of more than one byte write operation by one sequence.
After receipt of the third byte, the AK4128A generates an acknowledge, and awaits the next data again. The master can
transmit more than one word instead of terminating the write cycle after the first data word is transferred. After the receipt
of each data, the internal address counter is incremented by one, and the next data is taken into next address automatically.
If the address exceeds 03H prior to generating a stop condition, the address counter will “roll over” to 00H and the previous
data will be overwritten.
S
T
A Slave
R Address
T
Register
Address(n)
Data(n)
Data(n+1)
S
T
Data(n+x) _O
P
SD A
S
P
A
A
A
A
C
C
C
C
K
K
K
K
Figure 45. WRITE Operation
MS1242-E-00
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2010/09