AK4128A Datasheet, PDF (26/50 Pages) Asahi Kasei Microsystems – 8ch 216kHz / 24-Bit Asynchronous SRC

[AK4128A]
When the AK4128A is in master mode, SDTI1-4 data are input by the ILRCK1 and IBICK1 clocks in SRC bypass mode
(Table 2). The SDTI1-4 output data are output by the ILRCK1 and IBICK1 clocks in a format shown in Table 6 and Table
7. The ILRCK1 clock bypasses the SRC and it is output from the OLRCK pin. The IBICK1 clock bypasses the SRC and it
is output from the OBICK pin.
IBICK1
ILRCK1
SDTI1
IBICK2
ILRCK2
SDTI2
IBICK3
ILRCK3
SDTI3
Input
Serial
Audio
I/F
DEM
FIR
Bypass
SRC1
SRC
SRC
SMUTE
+
Dither _{0.5 LSB}
Bypass
SRC2
Input
Serial
Audio
DEM
FIR
SRC
SRC
SMUTE
+
I/F
Dither _{0.5 LSB}
Output
Serial
Audio
I/F
Input
Serial
Audio
I/F
DEM
FIR
Bypass
SRC3
SRC
SRC
SMUTE
+
Dither
0.5 LSB
OLRCK
OBICK
SDTO1
OBIT1
OBIT2
ODIF1
ODIF0
SDTO2
SDTO3
IBICK4
ILRCK4
SDTI4
IMCLK
PDN
PM1
PM2
Input
Serial
Audio
I/F
uP
I/F
DEM
FIR
Internal
OSC
Bypass
SRC4
SRC
SRC
SMUTE
+
Dither _{0.5 LSB}
Bypass
X’tal
Clock
Osc
Div
SRC
Internal
Regulator
REF
CAD0 SDA SCL XTO OMCLK/XTI ^{CM2 CM1 CM0}
SPB
VD18
SDTO4
UNLOCK
MCKO
AVDD
VSS1
Figure 24. Bypass Mode in Master Mode (Synchronous mode INAS pin = “L”)
MS1242-E-00
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2010/09