AK4128A Datasheet, PDF (15/50 Pages) Asahi Kasei Microsystems – 8ch 216kHz / 24-Bit Asynchronous SRC

Parameter
Symbol
min
typ
Control Interface Timing (I²C Bus):
SCL Clock Frequency
fSCL
-
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time
tHD:STA
0.6
(prior to first clock pulse)
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
0.6
SDA Hold Time from SCL Falling (Note 20) tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
0.1
Rise Time of Both SDA and SCL Lines
tR
-
Fall Time of Both SDA and SCL Lines
tF
-
Setup Time for Stop Condition
tSU:STO
0.6
Pulse Width of Spike Noise
tSP
0
Suppressed by Input Filter
Capacitive load on bus
Cb
-
Note 20. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
[AK4128A]
max
Units
400
kHz
-
μs
-
μs
-
μs
-
μs
-
μs
-
μs
-
μs
0.3
μs
0.3
μs
-
μs
50
ns
400
pF
MS1242-E-00
- 15 -
2010/09