AK4128A Datasheet, PDF (21/50 Pages) Asahi Kasei Microsystems – 8ch 216kHz / 24-Bit Asynchronous SRC

[AK4128A]
IDIF2 IDIF1 IDIF0
Mode Pin
Pin
Pin
(Note 23) (Note 23) (Note 23)
SDTI1-4 Format
ILRCK IBICK IBICK1-4
1-4
1-4
Freq
0
L
L
L
16bit, LSB justified
≥ 32FSI
1
L
L
H
20bit, LSB justified
≥ 40FSI
2
L
H
L
24bit, MSB justified
≥ 48FSI
3
L
H
H
24 or 16bit, I²S Compatible
16bit, I²S Compatible
Input
Input
≥ 48FSI
32FSI
4
H
L
L
24bit, LSB justified
≥ 48FSI
5
H
L
H TDM 24bit, MSB justified
6
H
H
X
TDM 24bit, I²S Compatible
256FSI
256FSI
Table 2. Input PORT Audio Interface Format (Parallel Control Mode, SPB pin= “L”) (X= Don’t care)
Note 23. In serial control mode (SPB pin = “H”), setting of IDIF2-0 pins is ignored. IDIF[12:10] bits setting is reflected to
SRC1, IDIF[22:20] bits setting is reflected to SRC2, IDIF[32:30] bits setting is reflected to SRC3, and
IDIF[42:40] bits setting is reflected to SRC4.
ILRCK
0123
IBICK(32fs)
9 10 11 12 13 14 15 0 1 2 3
9 10 11 12 13 14 15 0 1
SDTI(i)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
7 6 5 4 3 2 1 0 15
0123
IBICK(64fs)
17 18 19 20
31 0 1 2 3
17 18 19 20
31 0 1
SDTI(i)
Don't Care 15 14 13 12
15:MSB, 0:LSB
1 0 Don't Care 15 14 13 12
Lch Data
Rch Data
Figure 14. Mode 0 Timing (16bit, LSB justified)
210
ILRCK
012
IBICK(64fs)
12 13
24
31 0 1 2
12 13
24
SDTI(i)
Don't Care 19
8
19:MSB, 0:LSB
1 0 Don't Care 19
8
Lch Data
Rch Data
Figure 15. Mode 1 Timing (20bit, LSB justified)
31 0 1
10
ILRCK
012
IBICK(64fs)
20 21 22 23 24
31 0 1 2
20 21 22 23 24
31 0 1
SDTI(i)
23 22
4 3 2 1 0 Don't Care 23 22
4 3 2 1 0 Don't Care 23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 16. Mode 2 Timing (24bit, MSB justified)
MS1242-E-00
- 21 -
2010/09