AK4128A Datasheet, PDF (38/50 Pages) Asahi Kasei Microsystems – 8ch 216kHz / 24-Bit Asynchronous SRC

[AK4128A]
■ Serial Control Interface
The AK4128A supports fast-mode I²C-bus system (max: 400kHz). Pull-up resistors at SDA and SCL pins should be
connected to (DVDD1-4 + 0.3)V or less voltage.
1. Data transfer
All commands are preceded by a START condition. After the START condition, a slave address is sent. After the
AK4128A recognizes the START condition, the device interfaced to the bus waits of the slave address to be transmitted
over the SDA line. If the transmitted slave address matches an address for one of the devices, the designated slave device
pulls the SDA line to LOW (ACKNOWLEDGE). The data transfer is always terminated by a STOP condition generated by
the master device.
1-1. Data validity
The data on the SDA line must be stable during a HIGH period of the clock. The HIGH or LOW state of the data line can
only be changed when the clock signal on the SCL line is LOW except for the START and the STOP condition.
SCL
SDA
DATA LINE
STABLE :
DATA VALID
CHANGE
OF DATA
ALLOWED
Figure 39. Data Transfer
1-2. START and STOP condition
A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition. All sequences start from the
START condition.
A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. All sequences end by the
STOP condition.
S
SCL
SDA
START CONDITION
STOP CONDITION
Figure 40. START and STOP conditions
MS1242-E-00
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2010/09