AK4128A Datasheet, PDF (16/50 Pages) Asahi Kasei Microsystems – 8ch 216kHz / 24-Bit Asynchronous SRC

[AK4128A]
■ Timing Diagram
IMCLK(I)
OMCLK(I)
1/fECLK
tECLKH
tECLKL
1/fCLK
tCLKH
tCLKL
VIH
VIL
dECLK
= tECLKH (or tECLKL) x fECLK x 100
VIH
VIL
1/fMCK
MCKO(O)
tMCKH
tMCKL
50%DVDD
dMCLK
= tMCKH (or tMCKL) x fMCK x 100
Figure 5. IMCLK, OMCLK, MCKO Clock Timing
•Stereo Mode and Slave Mode
1/FSI
LRCK1-4(I)
tLRCH
tBCK
IBICK1-4(I)
tBCKH
tLRCL
VIH
VIL
Duty
= tLRCH (or tLRCL) x FSI x 100
VIH
VIL
tBCKL
•TDM256 Mode and Slave Mode
1/FSI
VIH
LRCK1(I)
VIL
tLRH
tLRL
tBCK
VIH
IBICK1(I)
VIL
tBCKH
tBCKL
Figure 6. ILRCK1-4, IBICK1-4 Clock Timing
MS1242-E-00
- 16 -
2010/09