AK4128A Datasheet, PDF (23/50 Pages) Asahi Kasei Microsystems – 8ch 216kHz / 24-Bit Asynchronous SRC

[AK4128A]
■ System Clock for Output PORT
The output ports work in master mode and slave mode. The CM2-0 pins select the master/slave mode.
Mode
CM2
pin
CM1
pin
CM0
pin
Master / Slave
OMCLK/XTI
Input
MCKO Output
FSO
FSO with
X’tal
0
LLL
Master
256FSO
256FSO 8k∼108kHz 44.1~96kHz
1
LLH
Master
384FSO
384FSO
8k∼96kHz 29.4~64kHz
2
LHL
Master
512FSO
512FSO
8k∼54kHz 22.05~48kHz
3
LHH
Master
768FSO
768FSO
8k∼48kHz 14.7~32kHz
4
HLL
Slave
Not used. (Note 24)
OMCLK Input
Clock
8k∼216kHz
-
5
HLH
Master
128FSO (Note 25)
128FSO 8k∼216kHz 88.2~192kHz
6
7
H
H
HL
HH
Slave(Bypass)
Master(Bypass)
Not used. (Note 24)
IMCLK Input
Clock
8k∼216kHz
-
Note 24. Use for a clock input or connect to VSS2-5 pin. In Mode 4, the MCKO pin outputs “L” if the OMCLK/XTI pin is
connected to VSS2-5. When a clock is input to the OMCLK/XTI pin, the clock is through and output from the
MCKO pin. In Mode 6-7, OMCLK/XTI input is ignored internally.
Note 25. Output ports do not support TDM mode in this mode.
Table 3. Output PORT Master/Slave/ Bypass Mode Control (SPB pin = “L”)
In serial control mode (SPB pin = “H”), the BYPS bit selects SRC bypass mode and SRC mode.
The default value of the BYPS bit is “0” (SRC mode).
Mode
CM2 CM1 CM0
pin pin pin
BYPS
bit
Master / Slave
OMCLK/XTI
Input
MCKO
Output
FSO
FSO with
X’tal
0
LLL
0
Master
256FSO
256FSO 8∼108kHz 44.1~96kHz
1
LLH
0
Master
384FSO
384FSO 8∼96kHz 29.4~64kHz
2
LHL
0
Master
512FSO
512FSO 8∼54kHz 22.05~48kHz
3
LHH
0
Master
768FSO
768FSO 8k~48kHz 14.7~32kHz
4
HLL
0
OMCLK
Slave
Not used. (Note 26) Input 8∼216kHz
-
Clock
5
HLH
0
Master
128FSO (Note 25) 128FSO 8∼216kHz 88.2~192kHz
6
HHL
0
Slave (Bypass)
7
HHH
0 Master (Bypass)
8
LLL
1 Master (Bypass)
9
10
11
LLH
LHL
LHH
1
1
1
Master (Bypass)
Master (Bypass)
Master (Bypass)
Not used. (Note 26)
IMCLK
Input
Clock
8∼216kHz
-
12 H L L
1
Slave (Bypass)
13
HLH
1
Master (Bypass)
14 H H L
1
Slave (Bypass)
15
HHH
1
Master (Bypass)
Note 26. Use for a clock input or connect to VSS2-5 pin. In Mode 4, the MCKO pin outputs “L” if the OMCLK/XTI pin is
connected to VSS2-5. When a clock is input to the OMCLK/XTI pin, the clock is through and output from the
MCKO pin. In Mode 6-15, OMCLK/XTI input is ignored internally.
Table 4. Output PORT Master/Slave/ Bypass Mode Control (SPB pin = “H”)
MS1242-E-00
- 23 -
2010/09