DSP16411 Datasheet, PDF (77/316 Pages) Agere Systems – DSP16411 Digital Signal Processor

Data Sheet
May 2003
DSP16411 Digital Signal Processor
4 Hardware Architecture (continued)
4.13 Direct Memory Access Unit (DMAU) (continued)
4.13.2 Registers (continued)
Table 37. SADD〈0—5〉 and DADD〈0—5〉 (Channels 0—5 Source and Destination Address) Registers
See Table 29, starting on page 67, for the memory addresses of these registers.
31—27
26—23
22—20
19—0
Reserved
ESEG[3:0] CMP[2:0]
ADD[19:0]
Bit
Field
31—27 Reserved
26—23 ESEG[3:0]
22—20 CMP[2:0]
19—0 ADD[19:0]
Value
Description
R/W Reset
Value^†
0
Reserved—write with zero.
R/W 0
0x0 External memory address extension. If the DMAU accesses external
R/W X
to
memory (CMP[2:0] = 100), it causes the SEMI to place the value in this
0xF field onto the ESEG[3:0] pins.
000 The selected memory component is TPRAM0.
R/W XXX
001 The selected memory component is TPRAM1.
R/W
01X Reserved.
R/W
100 The selected memory component is ERAM^‡, EIO, or internal I/O.
R/W
101 Reserved.
R/W
11X Reserved.
R/W
0x00000 The address within the selected memory component. For an MMT〈4—5〉 R/W X
to
channel, if the corresponding XSIZE[5:4] field (DMCON0[13:12]—see
0xFFFFF Table 31 on page 71) is set, this value must be even.
† For this column, X indicates unknown on powerup reset and unaffected on subsequent reset.
‡ If the WEROM field (ECON1[11]—Table 61 on page 112) is set, EROM is selected in place of ERAM.
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