DSP16411 Datasheet, PDF (43/316 Pages) Agere Systems – DSP16411 Digital Signal Processor

Data Sheet
May 2003
DSP16411 Digital Signal Processor
4 Hardware Architecture (continued)
4.6 Memory Maps (continued)
4.6.1 Private Internal Memory
Each core has its own private internal memories for
program and data storage. CORE0 has IROM0,
CACHE0, and TPRAM0. CORE1 has IROM1,
CACHE1, and TPRAM1. A core cannot directly access
the other core’s private memory. However, the DMAU
can access both TPRAM0 and TPRAM1 and can move
data between these two memories to facilitate core-to-
core communication (see Section 4.5 on page 38).
TPRAM is described in more detail in Section 4.7 on
page 48. Cache memory is described in detail in the
DSP16000 Digital Signal Processor Core Information
Manual. IROM contains boot and HDS code and is
described in Section 5 on page 208.
4.6.2 Shared Internal I/O
The 128 Kword internal I/O memory component is
accessible by both cores in their Y-memory spaces and
by the DMAU in its Z-memory space. Any access to
this memory component is made over the system bus
and is arbitrated by the SEMI. The internal shared I/O
memory component consists of:
! 2 Kwords of shared local memory (SLM). SLM can
be used for core-to-core communication (see
Section 4.5 on page 38). SLM is described in
Section 4.1.4 on page 17.
! Memory-mapped control and data registers within
the following peripherals:
— DMAU
— SEMI
— PIU
— SIU0
— SIU1
Only a small portion of the 128 Kwords reserved for
internal I/O is actually populated with memory or regis-
ters. Any access to the internal I/O memory compo-
nent takes multiple cycles to complete. DSP core or
DMAU writes take a minimum of two CLK cycles to
complete. DSP core or DMAU reads take a minimum
of five CLK cycles to complete.
4.6.3 Shared External I/O and Memory
External I/O and memory consists of three shared com-
ponents: EIO, ERAM, and EROM. EIO and ERAM are
accessible in the Y-memory spaces of both cores and
also in the DMAU’s Z-memory space. EROM is nor-
mally read-only and accessible only in the X-memory
spaces of both cores. If the programmer sets the
WEROM field in the memory-mapped ECON1 register
(see Table 61 on page 112), EROM takes the place of
ERAM in the Y-memory spaces of both cores and in
the DMAU’s Z-memory space (see Section 4.6.5 on
page 45 and Section 4.6.6 on page 46 for details).
This allows the EROM component to be written for pro-
gram downloads to external X memory.
The physical size of the EIO, ERAM, and EROM com-
ponents can be expanded from the sizes defined in
Table 15 on page 42 by employing the ESEG[3:0]
pins. The external memory system can use ESEG[3:0]
in either of the following ways:
1. ESEG[3:0] can be interpreted by the external mem-
ory system as four separate decoded address
enable signals. Each ESEG[3:0] pin individually
selects one of four segments for each memory
component. This results in four glueless 512 Kword
(1 Mbyte) ERAM segments, four glueless 512 Kword
(1 Mbyte) EROM segments, and four glueless
128 Kword (256 KB) EIO segments.
2. ESEG[3:0] can be interpreted by the external mem-
ory system as an extension of the address bus, i.e.,
the ESEG[3:0] pins can be concatenated with the
EAB[18:0] pins to form a 23-bit address. This results
in one glueless 8 Mword (16 Mbytes) ERAM seg-
ment, one glueless 8 Mword (16 Mbytes) EROM
segment, and one glueless 2 Mword (4 Mbytes) EIO
segment.
See Section 4.14.1.5 on page 106 for details on config-
uring the ESEG[3:0] pins.
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