DSP16411 Datasheet, PDF (5/316 Pages) Agere Systems – DSP16411 Digital Signal Processor

Data Sheet
May 2003
DSP16411 Digital Signal Processor
Table of Contents (continued)
Contents
Page
" 4.18.2 PLL LOCK Flag Generation ......................................................................................................201
" 4.18.3 PLL Registers ...........................................................................................................................202
" 4.18.4 PLL Programming Example ......................................................................................................203
" 4.18.5 Powering Down the PLL ...........................................................................................................203
" 4.18.6 Phase-Lock Loop (PLL) Frequency Accuracy and Jitter...........................................................203
" 4.19 External Clock Selection .....................................................................................................................204
" 4.20 Power Management............................................................................................................................205
" 5 Processor Boot-Up and Memory Download ...............................................................................................208
" 5.1 IROM Boot Routine and Host Download Via PIU ...............................................................................208
" 5.2 EROM Boot Routine and DMAU Download........................................................................................209
" 6 Software Architecture .................................................................................................................................210
" 6.1 Instruction Set Quick Reference .........................................................................................................210
" 6.1.1 Conditions Based on the State of Flags ....................................................................................226
" 6.2 Registers.............................................................................................................................................227
" 6.2.1 Directly Program-Accessible (Register-Mapped) Registers......................................................227
" 6.2.2 Memory-Mapped Registers.......................................................................................................231
" 6.2.3 Register Encodings ...................................................................................................................235
" 6.2.4 Reset States..............................................................................................................................249
" 6.2.5 RB Field Encoding ....................................................................................................................252
" 7 208-Ball PBGA Package Ball Assignments ................................................................................................253
" 8 Signal Descriptions .....................................................................................................................................256
" 8.1 System Interface .................................................................................................................................257
" 8.2 BIO Interface.......................................................................................................................................257
" 8.3 System and External Memory Interface..............................................................................................257
" 8.4 SIU0 Interface .....................................................................................................................................260
" 8.5 SIU1 Interface .....................................................................................................................................261
" 8.6 PIU Interface .......................................................................................................................................262
" 8.7 JTAG0 Test Interface ..........................................................................................................................263
" 8.8 JTAG1 Test Interface ..........................................................................................................................263
" 8.9 Power and Ground..............................................................................................................................264
" 9 Device Characteristics ................................................................................................................................265
" 9.1 Absolute Maximum Ratings ................................................................................................................265
" 9.2 Handling Precautions..........................................................................................................................265
" 9.3 Recommended Operating Conditions.................................................................................................265
" 9.3.1 Package Thermal Considerations .............................................................................................266
"10 Electrical Characteristics and Requirements ..............................................................................................267
" 10.1 Maintenance of Valid Logic Levels for Bidirectional Signals and Unused Inputs ................................268
" 10.1.1 Maintenance of Valid Logic Levels on the SEMI Interface ........................................................268
" 10.1.2 Maintenance of Valid Logic Levels on the PIU Interface...........................................................270
" 10.2 Analog Power Supply Decoupling.......................................................................................................271
" 10.3 Power Dissipation ...............................................................................................................................272
" 10.3.1 Internal Power Dissipation ........................................................................................................272
" 10.3.2 I/O Power Dissipation................................................................................................................273
" 10.4 Power Supply Sequencing..................................................................................................................275
" 11 Timing Charateristics and Requirements....................................................................................................276
" 11.1 Phase-Lock Loop ................................................................................................................................277
" 11.2 Wake-Up Latency ...............................................................................................................................278
" 11.3 DSP Clock Generation........................................................................................................................279
" 11.4 Reset Circuit .......................................................................................................................................280
" 11.5 Reset Synchronization ........................................................................................................................281
" 11.6 JTAG ...................................................................................................................................................282
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