DSP16411 Datasheet, PDF (244/316 Pages) Agere Systems – DSP16411 Digital Signal Processor

DSP16411 Digital Signal Processor
Data Sheet
May 2003
6 Software Architecture (continued)
6.2 Registers (continued)
6.2.3 Register Encodings (continued)
Table 162. psw0 (Processor Status Word 0) Register
15
14
13
12
11
10
9
8—5
4
3—0
LMI LEQ LLV LMV SLLV SLMV a1V
a1[35:32]
a0V
a0[35:32]
Bit
Field Value
Description
15
LMI
14
LEQ
13
LLV
12
LMV
11
SLLV
10
SLMV
9
a1V
8—5 a1[35:32]
4
a0V
3—0 a0[35:32]
0 Most recent DAU result^‡ is not negative.
1 Most recent DAU result^§ is negative (minus).
0 Most recent DAU result^§ is not zero.
1 Most recent DAU result^§ is zero (equal).
0 Most recent DAU operation^§ did not result in logical overflow.
1 Most recent DAU operation^§ resulted in logical overflow.^††
0 Most recent DAU operation did not result in mathematical overflow.
1 Most recent DAU operation^§ resulted in mathematical overflow.^‡‡
0 Previous DAU operation did not result in logical overflow.
1 Sticky version of LLV that remains active once set by a DAU operation until
explicitly cleared by a write to psw0.
0 Previous DAU operation did not result in mathematical overflow.
1 Sticky version of LMV that remains active once set by a DAU operation until
explicitly cleared by a write to psw0.
0 The current contents of a1 are not mathematically overflowed.
1 The current contents of a1 are mathematically overflowed.^§§
— Reflects the four lower guard bits of a1.^{††â€} 
0 The current contents of a0 are not mathematically overflowed.
1 The current contents of a0 are mathematically overflowed.^§§
— Reflects the four lower guard bits of a0.^{††â€} 
R/W
R/W
Reset
Value ^†
X
R/W
X
R/W
X
R/W
X
R/W
0
R/W
0
R/W
X
R/W XXXX
R/W
X
R/W XXXX
† In this column, X indicates unknown on powerup reset and unaffected on subsequent reset.
‡ ALU/ACS result or operation if the instruction uses the ALU/ACS; otherwise, ADDER or BMU result, whichever applies.
§ ALU/ACS result if the DAU operation uses the ALU/ACS; otherwise, ADDER or BMU result, whichever applies.
†† The ALU or ADDER cannot represent the result in 40 bits or the BMU control operand is out of range.
‡‡ The ALU/ACS, ADDER, or BMU cannot represent the result in 32 bits. For the BMU, other conditions can also cause mathematical overflow.
§§ The most recent DAU result that was written to that accumulator resulted in mathematical overflow (LMV) with FSAT = 0.
††† Required for compatibility with DSP16XX family.
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