DSP16411 Datasheet, PDF (265/316 Pages) Agere Systems – DSP16411 Digital Signal Processor

Data Sheet
May 2003
DSP16411 Digital Signal Processor
9 Device Characteristics
9.1 Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are
absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in
excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for
extended periods can adversely affect device reliability.
External leads can be bonded and soldered safely at temperatures of up to 235 °C.
Table 179. Absolute Maximum Ratings
Parameter
Voltage on VDD1 with Respect to VSS
Voltage on VDD1A with Respect to VSS
Voltage on VDD2 with Respect to VSS
Voltage on VDD2A with Respect to VSS
Voltage Range on Any Signal Pin^†
Junction Temperature (TJ)
Storage Temperature Range
Min
–0.3
–0.3
–0.3
–0.3
VSS – 0.3
–40
–40
Max
Unit
1.7
V
1.7
V
4.2
V
4.2
V
VDD2 + 0.3
V
VSS + 4.0
115
°C
150
°C
† During a transition, the voltage on an input pin can be outside the range of this specification for a short time duration (less than or equal to 1.0 ns). See
Table 183 on page 267 for details.
9.2 Handling Precautions
Although electrostatic discharge (ESD) protection circuitry has been designed into this device, proper precautions
must be taken to avoid exposure to ESD and electrical overstress (EOS) during all handling, assembly, and test
operations. Agere employs both a human-body model (HBM) and a charged-device model (CDM) qualification
requirement in order to determine ESD-susceptibility limits and protection design evaluation. ESD voltage thresh-
olds are dependent on the circuit parameters used in each of the models, as defined by JEDEC's JESD22-A114
(HBM) and JESD22-C101 (CDM) standards.
Table 180. Minimum ESD Voltage Thresholds
Device
DSP16411
Minimum HBM Threshold
2000 V
Minimum CDM Threshold
1000 V
9.3 Recommended Operating Conditions
Table 181. Recommended Operating Conditions
Maximum
Internal Clock
(CLK) Frequency^†
285 MHz
Minimum
Internal Clock
(CLK) Period T
3.5 ns
Junction
Temperature TJ (°C)
Min
Max
–40
115
Supply Voltage
VDD1, VDD1A (V)
Min
Max
1.15
1.25
Supply Voltage
VDD2 (V)
Min
Max
3.0
3.6
† The ratio of the instruction cycle rate (fCLK) to the input clock frequency (fCKI) is 1:1 without the PLL selected. With the PLL selected, the ratio of fCLK to
fCKI is the PLL output frequency (fSYN) and is determined by the programming of the PLL as defined in Table 4.18.1 on page 201. The maximum input
clock (CKI input pin) frequency is defined in Table 188 on page 277.
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