DSP16411 Datasheet, PDF (34/316 Pages) Agere Systems – DSP16411 Digital Signal Processor

DSP16411 Digital Signal Processor
Data Sheet
May 2003
4 Hardware Architecture (continued)
4.4.10 INT[3:0] and TRAP Pins
4.4 Interrupts and Traps (continued)
4.4.9 Software Interrupts
Software interrupts emulate hardware interrupts. A
software interrupt is always enabled and has no
assigned priority and no corresponding field in the ins
register. A program causes a software interrupt by exe-
cuting an icall IM6 instruction, where IM6 is replaced
with 0—63. When a software interrupt is serviced, the
core saves the contents of PC in the pi register and
transfers control to the interrupt vector defined in
Table 9 on page 33.
CAUTION: If a software interrupt is inserted into an
ISR, it is explicitly nested in the ISR and
therefore the ISR must be structured for
nesting. See Section 4.4.11 on page 35
for more information about nesting
interrupts.
The DSP16411 provides four positive-assertion edge-
detected interrupt pins (INT[3:0]) and a bidirectional
positive-assertion edge-detected trap pin (TRAP).
The TRAP pin is used by an application to gain control
of both processors for asynchronous event handling,
typically for catastrophic error recovery. It is a 3-state
bidirectional pin that connects to both cores and both
HDS blocks. TRAP is connected directly to both cores
via the PTRAP signal. After reset, TRAP is configured
as an input; it can be configured as an output under
JTAG control to support HDS multiple-device debug-
ging.
Figure 5 is a functional timing diagram for the INT[3:0]
and TRAP pins. A low-to-high transition of one of
these pins asserts the corresponding interrupt or trap.
INT[3:0] or TRAP must be held high for a minimum of
two CLK cycles and must be held low for at least two
CLK cycles before being reasserted. If INT[3:0] or
TRAP is asserted and stays high, the core services the
interrupt or trap only once.
A minimum of four cycles¹ after INT[3:0] or PTRAP is
asserted, the core services the interrupt or trap by exe-
cuting instructions starting at the vector location as
defined in Table 9 on page 33. In the case of PTRAP, a
maximum of three instructions are allowed to execute
before the core services the trap.
Functional Timing for INT[3:0] and TRAP
ECKO^†
INT[3:0]/TRAP^‡
A
B
† ECKO is programmed to be the internal clock CLK (the ECKOB[1:0] field (ECON1[3:2]—see Table 61 on page 112) which is programmed to
00 and the ECKOA[1:0] field (ECON1[1:0]) is programmed to 01).
‡ The INT[3:0] or TRAP pin must be held high for a minimum of two CLK cycles and must be held low for a minimum of two CLK cycles before
being reasserted.
Notes:
A. The DSP16411 synchronizes INT[3:0] or TRAP on the falling edge of the internal clock CLK.
B. A minimum four-cycle delay before the core services the interrupt or trap (executes instructions starting at the vector location). For a trap, the
core executes a maximum of three instructions before it services the trap.
Figure 5. Functional Timing for INT[3:0] and TRAP
1. The number of cycles depends on the number of wait-states incurred by the interrupted or trapped instruction.
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