DSP16411 Datasheet, PDF (134/316 Pages) Agere Systems – DSP16411 Digital Signal Processor

DSP16411 Digital Signal Processor
Data Sheet
May 2003
4 Hardware Architecture (continued)
4.14 System and External Memory Interface (SEMI) (continued)
4.14.7 Performance (continued)
4.14.7.4 Summary of Access Times (continued)
Tables 72 and 73 show example access times under various conditions, including DMAU accesses with SLKA = 0.
These access times are derived from actual measurements. For the asynchronous access times, it is assumed
that the programmed enable assertion time is one (ATIME = 1) and that RSETUP = RHOLD = WSETUP =
WHOLD = 0. The actual value of these fields is application-dependent. For the synchronous access times, it is
assumed that ECKO is programmed as CLK/2.
Table 72. Example Average Access Time Per SEMI Transaction, 32-Bit Data Bus
F
Requester
Access Type
Asynchronous
Synchronous (ECKO = CLK/2)
Reads
Writes
Reads
Writes
Core
16-bit
5 × TCLK
3 × TCLK
12 × TCLK
4 × TCLK
32-bit aligned
32-bit misaligned
10 × TCLK
6 × TCLK
24 × TCLK
8 × TCLK
DMAU, SLKA = 1
16-bit
2 × TCLK
3 × TCLK
4 × TCLK
4 × TCLK
32-bit aligned
DMAU, SLKA = 0
16-bit
9 × TCLK
5 × TCLK
14 × TCLK
5 × TCLK
32-bit aligned
Table 73. Example Average Access Time Per SEMI Transaction, 16-Bit Data Bus
Requester
Access Type
Core
DMAU, SLKA = 1
DMAU, SLKA = 0
16-bit
32-bit aligned
32-bit misaligned
16-bit
32-bit aligned
16-bit
32-bit aligned
Asynchronous
Reads
Writes
5 × TCLK
3 × TCLK
7 × TCLK
6 × TCLK
10 × TCLK
6 × TCLK
2 × TCLK
3 × TCLK
4 × TCLK
6 × TCLK
9 × TCLK
5 × TCLK
11 × TCLK
6 × TCLK
Synchronous (ECKO = CLK/2)
Reads
Writes
12 × TCLK
4 × TCLK
16 × TCLK
8 × TCLK
24 × TCLK
8 × TCLK
4 × TCLK
4 × TCLK
8 × TCLK
8 × TCLK
14 × TCLK
5 × TCLK
18 × TCLK
8 × TCLK
4.14.8 Priority
SEMI prioritizes the requests from both cores and the DMAU in the following order:
1. CORE0 program (X) and data (Y) requests have the highest priority. If CORE0 requires a simultaneous X and Y
access, X is performed first, then Y.
2. CORE1 program (X) and data (Y) requests have the second-highest priority. If CORE1 requires a simultaneous
X and Y access, X is performed first, then Y.
3. DMAU data requests have the lowest priority.
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