DSP16411 Datasheet, PDF (32/316 Pages) Agere Systems – DSP16411 Digital Signal Processor

DSP16411 Digital Signal Processor
Data Sheet
May 2003
4 Hardware Architecture (continued)
4.4 Interrupts and Traps (continued)
4.4.7 Hardware Interrupt Status
If a hardware interrupt occurs, the core sets the corre-
sponding bit in the ins register (Table 8) to indicate that
the interrupt is pending. If the core services the inter-
rupt, it clears the ins bit. Alternatively, if the application
uses interrupt polling (Section 4.4.13 on page 37), the
application program must explicitly clear the ins bit by
writing a 1 to that bit and a 0 to every other ins bit.
Writing a 0 to an ins bit leaves that bit unchanged. A
reset clears the ins register, indicating that no inter-
rupts are pending.
If a hardware interrupt occurs, the core sets its ins bit
(i.e., latches the interrupt as pending) regardless of
whether the interrupt is enabled or disabled. If a hard-
ware interrupt occurs while it is disabled and the inter-
rupt is later enabled, the core services the interrupt
after servicing any other pending interrupts of equal or
higher priority.
Note: The DSP16000 core globally disables interrupts
when it begins executing instructions in the vec-
tor table. If the ISR does not globally enable
interrupts by following the procedure specified in
Section 4.4.11 on page 35, Nesting Interrupts,
and the same interrupt reoccurs while the core is
executing the ISR, the interrupt is not latched
into ins and is therefore not recognized by the
core.
4.4.8 Interrupt and Trap Vector Table
The interrupt and trap vectors for a core are in contigu-
ous locations in memory. The base (starting) address
of the vectors is configurable in the core’s vbase
register. Each interrupt and trap source is pre-
assigned to a unique vector offset within a 352-word
vector table (see Table 9 on page 33). The program-
mer can place at the vector location an instruction that
branches to an interrupt service routine (ISR) or trap
service routine (TSR). After servicing the interrupt or
trap, the ISR or TSR must return to the interrupted or
trapped program by executing an ireturn or treturn
instruction. Alternatively, the programmer can place at
the vector location up to four words of instructions that
service the interrupt or trap, the last of which must be
an ireturn or treturn.
Table 8. ins (Interrupt Status) Register
19
MXI9
9
INT1
18
MXI8
8
INT0
17
MXI7
7
DMINT5
16
MXI6
6
DMINT4
15
MXI5
5
MXI3
14
MXI4
4
MXI2
13
PHINT
3
MXI1
12
XIO
2
MXI0
11
SIGINT
1
TIME1
10
MGIBF
0
TIME0
Field
Value
Description
MXI〈0—9〉^†
PHINT
XIO
SIGINT
MGIBF
INT〈0—1〉
DMINT〈4—5〉
TIME〈0—1〉
0
Read—corresponding interrupt not pending.
Write—no effect.
1
Read—corresponding interrupt is pending.
Write—clears bit and changes corresponding interrupt status to not
pending.
† See Table 5 on page 28 for definition of MXI〈0—9〉 (IMUX〈0—9〉).
R/W
R/Clear
Reset
Value
0
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