DSP16411 Datasheet, PDF (268/316 Pages) Agere Systems – DSP16411 Digital Signal Processor

DSP16411 Digital Signal Processor
Data Sheet
May 2003
10 Electrical Characteristics and Requirements (continued)
Table 183. Electrical Characteristics and Requirements (continued)
Pins
All outputs except ECKO
Output low (ECKO)
Output high (ECKO)
All 3-state outputs
All inputs
Parameter
Low-Output Voltage
High-Output Voltage
Low-Output Voltage
High-Output Voltage
Low-Output 3-State
Current
High-Output 3-State
Current
Input Capacitance
Symbol
VOL
VOH
VOL
VOH
IOZL
IOZH
CI
Condition
IOL = 4.0 mA
IOL = 50 µA
IOH = –4.0 mA
IOH = –50 µA
(IOL = 4.0 mA)
(IOL = 100 µA)
(IOH = – 4.0 mA)
(IOH = – 100 µA)
VIL = 0 V,
VDD2 = 3.6 V
VIH = VDD2,
VDD2 = 3.6 V
—
Min
—
—
2.4
VDD2 – 0.2
—
—
VDD2 –0.7
VDD2 – 0.2
–10
—
—
Max
0.4
0.2
—
—
0.4
0.2
—
—
—
10
5
Unit
V
V
V
V
V
V
V
V
µA
µA
pF
10.1 Maintenance of Valid Logic Levels for Bidirectional Signals and Unused Inputs
Except for the SEMI and PIU data and address bus pins, the DSP16411 does not include any internal circuitry to
maintain valid logic levels on input pins or on bidirectional pins that are not driven. For correct device operation and
low static power dissipation, valid CMOS levels must be applied to these input and bidirectional pins. Failure to
ensure full CMOS levels (VIL or VIH) on pins that are not driven may result in high static power consumption and
possible device failure.
Any unused input pin must be pulled up to the I/O pin supply (VDD2) or pulled down to VSS according to the func-
tional requirements of the pin. The pin can be pulled up or down directly or through a 10 kΩ resistor. Any unused
bidirectional pin, statically configured as an input, should be pulled to VDD2 or VSS through a 10 kΩ resistor.
10.1.1 Maintenance of Valid Logic Levels on the SEMI Interface
The SEMI data and address buses (ED[31:0], EA[18:0], and ESEG[3:0]) include internal bus hold circuits that are
enabled during reset and are enabled by default after reset. These bus hold circuits can be disabled by setting the
BHEDIS field (ECON1[12]—Table 61 on page 112). If the bus hold circuits are enabled, external pull-up/down
resistors are not needed on ED[31:0], EA[18:0], or ESEG[3:0].
If the SEMI interface is unused in the system, the EYMODE pin can be connected to VDD2 to force the internal data
bus transceivers on ED[31:0] to always be in the output mode. If the SEMI interface is used in the system, the
EYMODE pin must be connected to VSS.
268
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