DSP16411 Datasheet, PDF (229/316 Pages) Agere Systems – DSP16411 Digital Signal Processor

Data Sheet
May 2003
DSP16411 Digital Signal Processor
6 Software Architecture (continued)
6.2 Registers (continued)
6.2.1 Directly Program-Accessible (Register-Mapped) Registers (continued)
Table 139. Program-Accessible (Register-Mapped) Registers by Type, Listed Alphabetically
Register Name
Description
Size _R/W^† _Type^‡ _Signed^§_/ Core/ Function
(Bits)
Unsigned Off-Core Block
a0, a1, a2, a3, a4, a5, a6, a7 Accumulators 0—7
40 R/W data signed
core
DAU
a0h, a1h, a2h, a3h,
a4h, a5h, a6h, a7h
Accumulators 0—7,
high halves (bits 31—16)
16 R/W data signed
core
DAU
a0l, a1l, a2l, a3l,
a4l, a5l, a6l, a7l
Accumulators 0—7,
low halves (bits 15—0)
16 R/W data signed
core
DAU
a0g, a1g, a2g, a3g,
a4g, a5g, a6g, a7g
Accumulators 0—7,
guard bits (bits 39—32)
8 R/W data signed
core
DAU
a0_1h, a2_3h,
a4_5h, a6_7h
Accumulator vectors
(concatenated high halves
of two adjacent accumulators)
32 R/W data signed
core
DAU
alf
AWAIT and flags
16 R/W c & s unsigned core
SYS
ar0, ar1, ar2, ar3
Auxiliary registers 0—3
16 R/W data signed
core
DAU
auc0, auc1
Arithmetic unit control
16 R/W c & s unsigned core
DAU
c0, c1
Counters 0 and 1
16 R/W data signed
core
DAU
c2
Counter holding register
16 R/W data signed
core
DAU
cbit
BIO control
16 R/W control unsigned off-core BIO
cloop
Cache loop count
16 R/W data unsigned core
SYS
csave
Cache save
32 R/W control unsigned core
SYS
cstate
Cache state
16 R/W control unsigned core
SYS
h
Pointer postincrement
20 R/W data signed
core
XAAU
i
Pointer postincrement
20 R/W data signed
core
XAAU
imux
Interrupt multiplex control
16 R/W control unsigned off-core IMUX
inc0, inc1
Interrupt control 0 and 1
20 R/W control unsigned core
SYS
ins
Interrupt status
20 R/C^†† status unsigned core
SYS
j
Pointer postincrement/offset
20 R/W data signed
core
YAAU
jhb
High byte of j (bits 15—8)
8
R data unsigned core
YAAU
jlb
Low byte of j (bits 7—0)
8
R data unsigned core
YAAU
jiob
JTAG test
32 R/W data unsigned off-core JTAG
k
Pointer postincrement/offset
20 R/W data signed
core
YAAU
mgi
Core-to-core message input
16 R data unsigned off-core MGU
mgo
Core-to-core message output
16 W data unsigned off-core MGU
p0
Product 0
32 R/W data signed
core
DAU
p0h
High half of p0 (bits 31—16)
16 R/W data signed
core
DAU
p0l
Low half of p0 (bits 15—0)
16 R/W data signed
core
DAU
p1
Product 1
32 R/W data signed
core
DAU
p1h
High half of p1 (bits 31—16)
16 R/W data signed
core
DAU
p1l
Low half of p1 (bits 15—0)
16 R/W data signed
core
DAU
pi
Program interrupt return
20 R/W address unsigned core
XAAU
pid
Processor identification
16 R c & s unsigned off-core MGU
† R indicates that the register is readable by instructions; W indicates the register is writable by instructions.
‡ c & s means control and status.
§ Signed registers are in two’s complement format.
†† C indicates that the register is cleared and not set.
‡‡ The IEN field (bit 14) of the psw1 register is read only (writes to this bit are ignored).
§§ The VALUE[6:0] field (bits 6—0) are read only (writes to these bits are ignored).
Agere Systems Inc.
Agere Systems—Proprietary
229
Use pursuant to Company instructions