DSP16411 Datasheet, PDF (30/316 Pages) Agere Systems – DSP16411 Digital Signal Processor

DSP16411 Digital Signal Processor
Data Sheet
May 2003
4 Hardware Architecture (continued)
4.4 Interrupts and Traps (continued)
4.4.3 Clearing Core Interrupt Requests
Internal hardware interrupt signals are pulses that the core latches into its ins register (see Section 4.4.7 on
page 32). Therefore, the user software need not clear the interrupt request. However, in the case of the PIU host
interrupt, PHINT, the user software must clear the HINT field (PCON[4]) to allow the host to request a subsequent
interrupt. See Section 4.15.7 on page 153 for details.
4.4.4 Host Interrupt Output
The DSP16411 provides an interrupt output pin, PINT, that can interrupt a host processor connected to the PIU. A
core can assert this pin by setting the PINT field (PCON[3]). The host must clear the PINT field to allow a core to
request a subsequent interrupt. See Section 4.15.7 on page 153 for details.
4.4.5 Globally Enabling and Disabling Hardware Interrupts
A device reset globally disables interrupts, i.e., the core does not service interrupts by default after reset. The
application must execute an ei instruction to globally enable interrupts, i.e., to cause the core to service interrupts
that are individually enabled. Section 4.4.6 on page 31 describes individually enabling and disabling
interrupts. Executing the di instruction globally disables interrupts.
The core automatically globally disables interrupts if it begins servicing an interrupt, i.e., interrupt nesting is dis-
abled by default. When the ireturn instruction that the programmer must place at the end of the ISR is executed,
the core automatically globally re-enables interrupts. Therefore, the programmer does not need to explicitly re-
enable interrupts by executing an ei instruction before exiting the ISR. An interrupt service routine (ISR) can allow
nesting, i.e., can be interrupted by a higher-priority interrupt, if it globally enables interrupts in the correct sequence
as described in Section 4.4.11 on page 35, Nesting Interrupts.
The one-bit IEN field (psw1[14]—see Table 10 on page 35) is cleared if hardware interrupts are globally
disabled. The IEN field is set if interrupts are globally enabled.
Table 6 summarizes global disabling and enabling of hardware interrupts.
Table 6. Global Disabling and Enabling of Hardware Interrupts
Condition
Hardware interrupts
globally^† disabled
Caused By
! Device reset
! Execution of a di instruction
Indicated By
IEN (psw1[14]) = 0
Effect
Core does not service
interrupts.
Hardware interrupts
globally^† enabled
! The core begins to service an interrupt
! Execution of an ei instruction
! Execution of an ireturn instruction
IEN (psw1[14]) = 1
Core services individually
enabled interrupts.
† With the exception of device reset, CORE0 and CORE1 are independent with respect to global disabling and enabling of hardware interrupts.
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