DSP16411 Datasheet, PDF (73/316 Pages) Agere Systems – DSP16411 Digital Signal Processor

Data Sheet
May 2003
DSP16411 Digital Signal Processor
4 Hardware Architecture (continued)
4.13 Direct Memory Access Unit
(DMAU) (continued)
4.13.2 Registers (continued)
Table 34 on page 74 describes the SWT〈0—3〉 control
registers, CTL〈0—3〉. Each of the CTL〈0—3〉 registers
controls the behavior of the corresponding SWT chan-
nel and determines the following:
1. Whether the access takes place in row-major (two-
dimensional array) or column-major (one-dimen-
sional array) order.
2. Whether the autoload feature is enabled or disabled.
If enabled, this feature causes the DMAU to auto-
matically reload the address registers with the con-
tents of the base register after an entire array has
been processed.
3. The point in the operation when a DMAU interrupt
request is generated.
The control register for a specific SWT channel deter-
mines these attributes for both the source and destina-
tion transfers for that channel. Therefore, if the SWT
channel is used for bidirectional transfers, the source
and destination data must have the same array size
and structure. As a result, each SWT channel has only
one stride (STR〈0—3〉) and one reindex (RI〈0—3〉)
register. Therefore, references to fields in Table 34 are
common to both SWT source and destination transfers
and are given as common references. Table 33 maps
the common references used in Table 34 to their spe-
cific attribute.
Table 33. Collective Designations Used in Table 34
Collective
Designation
RUN
ADD
Description
Source Channel Enable for SWT〈3—0〉
Destination Channel Enable for SWT〈3—0〉
Source Address
Destination Address
ROW
Source Row Counter
Destination Row Counter
COL
Source Column Counter
Destination Column Counter
LASTROW
Row Limit
LASTCOL
Column Limit
BAS
Source Base Register
Destination Base Register
STR
Stride Register
RI
Reindex Register
Register or Register Field
See
SRUN[3:0] (DMCON0[3:0])
DRUN[3:0] (DMCON0[7:4])
SADD〈0—3〉
DADD〈0—3〉
SROW[12:0] (SCNT〈0—3〉[19:7])
DROW[12:0] (DCNT〈0—3〉[19:7])
SCOL[6:0] (SCNT〈0—3〉[6:0])
DCOL[6:0] (DCNT〈0—3〉[6:0])
LASTROW[12:0] (LIM〈0—3〉[19:7])
LASTCOL[6:0] (LIM〈0—3〉[6:0])
SBAS〈0—3〉
DBAS〈0—3〉
STR〈0—3〉
RI〈0—3〉
Table 31 on page 71
Table 37 on page 77
Table 38 on page 78
Table 40 on page 79
Table 38 on page 78
Table 40 on page 79
Table 42 on page 80
Table 44 on page 81
Table 45 on page 81
Table 46 on page 82
Table 47 on page 82
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