DSP16411 Datasheet, PDF (133/316 Pages) Agere Systems – DSP16411 Digital Signal Processor

Data Sheet
May 2003
DSP16411 Digital Signal Processor
4 Hardware Architecture (continued)
4.14 System and External Memory Interface (SEMI) (continued)
4.14.7 Performance (continued)
4.14.7.4 Summary of Access Times
Tables 68 through 71 summarize the information in Section 4.14.7.2, beginning on page 129, and Section 4.14.7.3,
beginning on page 131.
Table 68. Access Time Per SEMI Transaction, Asynchronous Interface, 32-Bit Data Bus
F
Requester Access Type
Reads
Writes
Core
16-bit
[ATIME + 4 + RSETUP + RHOLD] × TCLK
[ATIME + 2 + WSETUP + WHOLD] × TCLK
32-bit aligned
32-bit misaligned [ATIME + 4 + RSETUP + RHOLD] × 2 × TCLK [ATIME + 2 + WSETUP + WHOLD] × 2 × TCLK
DMAU,
SLKA = 1
16-bit
32-bit aligned
[ATIME + 1 + RSETUP + RHOLD] × TCLK
[ATIME + 2 + WSETUP + WHOLD] × TCLK
Table 69. Access Time Per SEMI Transaction, Asynchronous Interface, 16-Bit Data Bus
F
Requester Access Type
Reads
Writes
Core
16-bit
[ATIME + 4 + RSETUP + RHOLD] × TCLK
[ATIME + 2 + WSETUP + WHOLD] × TCLK
32-bit aligned
[ATIME + 6 + RSETUP + RHOLD] × TCLK [ATIME + 2 + WSETUP + WHOLD] × 2 × TCLK
32-bit misaligned [ATIME + 4 + RSETUP + RHOLD] × 2 × TCLK [ATIME + 2 + WSETUP + WHOLD] × 2 × TCLK
DMAU,
SLKA = 1
16-bit
[ATIME + 1 + RSETUP + RHOLD] × TCLK
[ATIME + 2 + WSETUP + WHOLD] × TCLK
32-bit aligned [ATIME + 1 + RSETUP + RHOLD] × 2 × TCLK [ATIME + 2 + WSETUP + WHOLD] × 2 × TCLK
Table 70. Access Time Per SEMI Transaction, Synchronous Interface, 32-Bit Data Bus
F
Requester
Access Type
Reads
Writes
CLK/2^†
CLK/4^†
CLK/2^†
Core
16-bit
12 × TCLK
20 × TCLK
4 × TCLK
32-bit aligned
32-bit misaligned
24 × TCLK
40 × TCLK
8 × TCLK
DMAU,
SLKA = 1
16-bit
32-bit aligned
4 × TCLK
8 × TCLK
4 × TCLK
CLK/4^†
8 × TCLK
16 × TCLK
8 × TCLK
† Value of ECKO, depending on the programming of the ECKOB[1:0] and ECKOA[1:0] fields of ECON1—Table 61 on page 112.
Table 71. Access Time Per SEMI Transaction, Synchronous Interface, 16-Bit Data Bus
F
Requester
Access Type
Reads
Writes
CLK/2^†
CLK/4^†
CLK/2^†
Core
16-bit
12 × TCLK
20 × TCLK
4 × TCLK
32-bit aligned
16 × TCLK
24 × TCLK
8 × TCLK
32-bit misaligned
24 × TCLK
40 × TCLK
8 × TCLK
DMAU,
SLKA = 1
16-bit
32-bit aligned
4 × TCLK
8 × TCLK
8 × TCLK
16 × TCLK
4 × TCLK
8 × TCLK
CLK/4^†
8 × TCLK
16 × TCLK
16 × TCLK
8 × TCLK
16 × TCLK
† Value of ECKO, depending on the programming of the ECKOB[1:0] and ECKOA[1:0] fields of ECON1—Table 61 on page 112.
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