DSP16411 Datasheet, PDF (196/316 Pages) Agere Systems – DSP16411 Digital Signal Processor

DSP16411 Digital Signal Processor
Data Sheet
May 2003
4 Hardware Architecture (continued)
4.16 Serial Interface Unit (SIU) (continued)
4.16.15 Registers (continued)
Table 116. SIDR (SIU Input Data) Register
The memory address for this register is 0x4301A for SIU0 and 0x4401A for SIU1.
15—0
Serial Input Data
Bit
15—0
Field
Serial Input Data
Description
R/W
Read-only 16-bit serial input data. The SIU can optionally expand the R
data in the input shift register before latching it into SIDR. The user
program controls this optional expansion by configuring the IFOR-
MAT[1:0] field (SCON0[1:0]—Table 103 on page 185).
Reset Value
0
Table 117. SODR (SIU Output Data) Register
The memory address for this register is 0x4301C for SIU0 and 0x4401C for SIU1.
15—0
Serial Output Data
Bit
Field
Description
R/W Reset Value
15—0 Serial Output Data Write-only 16-bit serial output data. The SIU optionally compresses
W
0
the data in SODR before latching it into the output shift register. The
user program controls this optional compression by configuring the
OFORMAT[1:0] field (SCON0[9:8]—Table 103 on page 185).
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