DSP16411 Datasheet, PDF (70/316 Pages) Agere Systems – DSP16411 Digital Signal Processor

DSP16411 Digital Signal Processor
Data Sheet
May 2003
4 Hardware Architecture (continued)
4.13 Direct Memory Access Unit (DMAU) (continued)
4.13.2 Registers (continued)
Table 30. DSTAT (DMAU Status) Register (continued)
Bits Field Value
Description
R/W Reset
Value^†
17 SRDY3 1 SWT3 has a source transaction pending.
R
X
0 SWT3 does not have a source transaction pending.
16 DRDY3 1 SWT3 has a destination transaction pending.
R
X
0 SWT3 does not have a destination transaction pending.
15 ERR3
1 SWT3 has detected a protocol error (source or destination). Error report is cleared by R/Clear X
writing a 1 to this bit.
0 SWT3—no errors.
14 SBSY2 1 SWT2 is reading memory.
R
X
0 SWT2 is not reading memory.
13 DBSY2 1 SWT2 is writing memory.
R
X
0 SWT2 is not writing memory.
12 SRDY2 1 SWT2 has a source transaction pending.
R
X
0 SWT2 does not have a source transaction pending.
11 DRDY2 1 SWT2 has a destination transaction pending.
R
X
0 SWT2 does not have a destination transaction pending.
10 ERR2
1 SWT2 has detected a protocol error (source or destination). Error report is cleared by R/Clear X
writing a 1 to this bit.
0 SWT2—no errors.
9 SBSY1 1 SWT1 is reading memory.
R
X
0 SWT1 is not reading memory.
8 DBSY1 1 SWT1 is writing memory.
R
X
0 SWT1 is not writing memory.
7 SRDY1 1 SWT1 has a source transaction pending.
R
X
0 SWT1 does not have a source transaction pending.
6 DRDY1 1 SWT1 has a destination transaction pending.
R
X
0 SWT1 does not have a destination transaction pending.
5 ERR1
1 SWT1 has detected a protocol error (source or destination). Error report is cleared by R/Clear X
writing a 1 to this bit.
0 SWT1—no errors.
4 SBSY0 1 SWT0 is reading memory.
R
X
0 SWT0 is not reading memory.
3 DBSY0 1 SWT0 is writing memory.
R
X
0 SWT0 is not writing memory.
2 SRDY0 1 SWT0 has a source transaction pending.
R
X
0 SWT0 does not have a source transaction pending.
1 DRDY0 1 SWT0 has a destination transaction pending.
R
X
0 SWT0 does not have a destination transaction pending.
0 ERR0
1 SWT0 has detected a protocol error (source or destination). Error report is cleared by R/Clear X
writing a 1 to this bit.
0 SWT0—no errors.
† For this column, X indicates unknown on powerup reset and unaffected on subsequent reset.
‡ A core resets MMT5 by setting the RESET5 field (DMCON1[5]—Table 32 on page 72) and resets MMT4 by setting the RESET4 field (DMCON1[4]).
70
Agere Systems—Proprietary
Agere Systems Inc.
Use pursuant to Company instructions