Z87100 Datasheet, PDF (35/48 Pages) Zilog, Inc. – Wireless Transmitter

Zilog
R245 PRE0
D7 D6 D5 D4 D3 D2 D1 D0
Count Mode
0 T0 Single Pass
1 T0 Modulo N
X
Prescaler Modulo
(Range: 1-64 Decimal
01-00 HEX)
Figure 34. Prescaler 0 Register
(F5H: Write Only)
PNCON (C) 00
D7 D6 D5 D4 D3 D2 D1 D0
PN_ENABLE
0 Disable
1 Enable
REF_CLOCK_SELECT
00 SCLK
01 T0
1X T1
PNCLKOUT_ENABLE
0 P36 I/O
1 P36 PNCLKOUT
PNDOUT_ENABLE
0 P20 I/O
1 P20 DCLKOUT
PNDCLKOUT_ENABLE
0 P27 I/O
1 P27 PNDCLKOUT
PN_MODULATE
0 STOP
1 START
DATA_CLOCK_MODE
0 PNLEN-dependent data clock
1 Independent data clock
Note: Register settings are not reset upon Stop-Mode Recovery.
Figure 35. PN Modulator Control Register
((C) 00H: Read/Write)
PNADDR (C) 01
D7 D6 D5 D4 D3 D2 D1 D0
PNADDR = PN sequence
starting address
Note: Register settings are not reset upon Stop-Mode Recovery.
Figure 36. PN ROM Relative Address Register
((C) 01H: Read/Write)
Z87100
Wireless Transmitter
PNLEN (C) 02
D7 D6 D5 D4 D3 D2 D1 D0
3
PNLEN = PN sequence length
Note: Register settings are not reset upon Stop-Mode Recovery.
Figure 37. PN Code Length Register
((C) 02H: Read/Write)
TxBUFH (C) 04
D7 D6 D5 D4 D3 D2 D1 D0
TxBUFH = X
Note: Register settings are not reset upon Stop-Mode Recovery.
Figure 38. PN Modulator Low-Byte
Data Hold Register ((C) 03H: Write Only)
TxBUFH (C) 04
D7 D6 D5 D4 D3 D2 D1 D0
TxBUFH = X
Note: Register settings are not reset upon Stop-Mode Recovery.
Figure 39. PN Modulator High-Byte
Data Hold Register ((C) 04H: Write Only)
DCLK (C) 05
D7 D6 D5 D4 D3 D2 D1 D0
When DATA_CLOCK_MODE
(PNCON D7) = 0,
dataclk = refclk/2D1-D0
D2 = 0: pnclk = refclk
D2 = 1: pnclk = refclk/4
When DATA_CLOCK_MODE
(PNCON D7) = 1,
pnclk = refclk
dataclk = refclk/DCLK
Note: Register settings are not reset upon Stop-Mode Recovery.
Figure 40. Data Clock Control Register
((C) 05H: Read/Write)
DS96WRL0700
PRELIMINARY
3-35