Z87100 Datasheet, PDF (30/48 Pages) Zilog, Inc. – Wireless Transmitter

Z87100
Wireless Transmitter
FUNCTIONAL DESCRIPTION (Continued)
Watch-Dog Timer Mode Register (WDTMR). The WDT
is a retriggerable one-shot timer that resets the Z8 if it
reaches its terminal count. The WDT is initially enabled by
executing the WDT instruction and retriggered on subse-
quent executions of the WDT instruction. The WDT timer
circuit is driven by an on-board WDT oscillator or external
clock source RC. The WDT does not use TMBASE. The
WDT timer clock source is selected with bit 4 of the WDT-
MR to use either the internal WDT oscillator and a reset
delay of 5 ms, or RC1 and a reset delay of 512 RC1 clock
cycles. Note that the WDT instruction may affect the zero,
sign, and overflow flags.
Bits 0 and 1 control a tap circuit that determines the WDT
time-out period. Bit 2 determines whether the WDT is ac-
tive during HALT and bit 3 determines WDT activity during
Zilog
STOP. If bits 3 and 4 of this register are both set to 1, only
the WDT is only driven by the external clock during STOP
mode. This feature makes it possible to wake up from
STOP mode from an internal source. Bits 5 through 7 of
the WDTMR are reserved (Figure 23).
The WDTMR register is accessible only during the first 64
processor cycles (128 oscillator clocks) from the execution
of the first instruction after Power-On-Reset, Watch Dog
Reset or a Stop-Mode Recovery (Figure 22). After this
point, the register cannot be modified by any means, inten-
tional or otherwise. The WDTMR cannot be read and is lo-
cated in bank F of the Expanded Register Group at ad-
dress location 0FH, as shown in Figure 23.
VDD
SMR D4 D3 D2
000
001
SMR D4 D3 D2
011
XTALB
P20
Time Base
Generator
P27
SMR D4 D3 D2
010
P20
P31
P23
SMR D4 D3 D2
111
Stop Mode Recovery
Edge Select (SMR)
P33 From Pads
SMR D4 D3 D2
110
Digital/Analog Mode
Select (P3M)
SMR D4 D3 D2
100
P33
SMR D4 D3 D2
101
P27
To POR
Reset
To P33 Data
Latch and IRQ1
MUX
Figure 22. Stop-Mode Recovery Source
Note: The POR, with TMBASE the default Z8 clock
source, takes 1.5 seconds the first instruction is exe-
cuted by the Z8.
3-30
PRELIMINARY
DS96WRL0700