Z87100 Datasheet, PDF (31/48 Pages) Zilog, Inc. – Wireless Transmitter

Zilog
Z87100
Wireless Transmitter
WDT Time Select (D1,D0). Selects the WDT time-out pe- Notes: The internal clock frequency is one half the
riod. It is configured as shown in Table 9.
external clock frequency, unless the device is divide-by-
Table 9. WDT Time Select
one mode.
3
The device functions normally at or above 3.0V under all
Time-out of
conditions. Below 3.0V, the device functions normally until
D1
D0
internal WDT Time-out of
OSC
RC7 clock
the Low-Voltage Protection trip point (V_LV) is reached, for
the temperatures and operating frequencies described
0
0
5 ms min
512TpC
above. The device is guaranteed to function normally at
0
1
15 ms min
1024TpC
supply voltages above the low voltage trip point. The actu-
1
0
25 ms min
2048TpC
al low voltage trip point is a function of temperature and
process parameters (Figure 23).
1
1
100 ms min
8192TpC
Note: The default on a WDT initiated RESET is 15 ms.
WDT During HALT (D2). This bit determines whether or
not the WDT is active during HALT mode. A 1 indicates ac-
tive during HALT. The default is 1.
ROM Protect. ROM protect is mask-programmable. It is
selected by the customer at the time the ROM code is sub-
mitted. The selection of ROM protect disables the LDC and
LDCI instructions.
WDT During STOP (D3). This bitdetermines whether or
not the WDT is active during STOP mode. A 1 indicates
active during STOP. The default is 1. If bits D3 and D4 are
both set to 1, then only the WDT is driven by the external
clock during STOP mode.
On-Board WDT Oscillator or RC Oscillator Select (D4).
This bit determines which oscillator source is used to clock
the internal recovery and WDT counter chain. If the bit is a
1, the internal WDT oscillator is bypassed and the recovery
and WDT clock source is driven from RC1. The default
configuration of this bit is 0, which selects the internal WDT
oscillator.
WDTMR (F) 0F
D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP
00
01
10
11
INT WDT OSC
5
15
25
100
RC7 CLK
512 TpC
1024 TpC*
2048 TpC
8192 TpC
WDT During HALT
0 OFF
1 ON *
WDT During STOP
0 OFF
1 ON *
RC/WDT OSC Select for WDT
0 WDT Oscillator_*
1 RC7 Oscillator
Reserved (Must be 0)
V_CC Voltage Comparator. An on-board Voltage Compar-
ator checks that V_CC is at the required level to ensure cor-
rect operation of the device. Reset is globally driven if V_CC
is below the specified voltage (typically 2.1V).
* Default setting after RESET
Figure 23. Watch-Dog Timer Mode Register
Low-Voltage Protection (V_LV). The low voltage trip volt-
age (V_LV) will be less than 3 volts and above 1.4 volts un-
der the following conditions.
Maximum (V_LV) Conditions:
T_A = 0°, +70°C, Internal Clock Frequency
equal or less than 2 MHz
DS96WRL0700
PRELIMINARY
3-31