Z87100 Datasheet, PDF (14/48 Pages) Zilog, Inc. – Wireless Transmitter

Z87100
Wireless Transmitter
FUNCTIONAL DESCRIPTION
The Z8^® Wireless Controller incorporates special func-
tions to enhance the Z8’s application in consumer, auto-
motive, industrial, scientific research, and advanced tech-
nology applications.
RESET. The device can be reset through one of the follow-
ing mechanisms:
s Power-On Reset
s Watch-Dog Timer
s Stop-Mode Recovery Source
The device does not re-initialize the WDTMR, SMR, P2M,
or P3M registers to their reset values on a Stop-Mode Re-
covery operation.
Program Memory. The Z87100 can address up to 1
Kbytes of internal program memory (Figure 10). The first
12 bytes of program memory are reserved for the interrupt
vectors. These locations contain six 16-bit vectors that cor-
respond to the six available interrupts. Byte 13 to byte
1023 consists of on-chip, mask-programmed ROM.
ROM Protect. The 1 Kbytes of Program Memory are mask
programmable. A ROM protect feature will prevent “dump-
ing” of the ROM contents by inhibiting execution of the
LDC and LDCI instructions to program memory in all
modes.
Expanded Register File. The register file has been ex-
panded to allow for additional system control registers and
for mapping of additional peripheral devices and input/out-
put ports into the register address area. The Z8 register
address space R0 through R15 is implemented as 16
groups of 16 registers per group. These register groups
are known as the ERF (Expanded Register File). Bits 3-0
of the Register Pointer (RP) select the active ERF group.
Bits 7-4 of register RP select the working register group
(Figure 11). Three system configuration registers reside in
the Expanded Register File address space in Bank F,
while six PN modulator registers reside in Bank C. The rest
of the Expanded Register addressing space is not physi-
cally implemented and is open for future expansion. To
write to the ERF, the upper nibble of the RP must be zero.
To write to the rest of the register file, the lower nibble must
be zero.
Zilog
Antiheroine using Zilog's cross assembler Version 2.1 or
earlier, use theLD RP, #0X instruction rather than the SRP
#0X instruction to access the ERF.
1023
Location of
First Byte of
Instruction
Executed
After RESET 12
11
10
9
8
7
Interrupt
Vector ₆
(Lower Byte)
5
4
Interrupt
Vector ₃
(Upper Byte)
2
1
0
On-Chip
ROM
IRQ5
IRQ5
IRQ4
IRQ4
IRQ3
IRQ3
IRQ2
IRQ2
IRQ1
IRQ1
IRQ0
IRQ0
Figure 10. Program Memory Map
3-14
PRELIMINARY
DS96WRL0700