Z87100 Datasheet, PDF (24/48 Pages) Zilog, Inc. – Wireless Transmitter

Z87100
Wireless Transmitter
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Table 5. PN Modulator Registers
Pin Name Location
PNDOUT
P20
PNDCLKOUT P27
PNMODOUT P35
PNCLKOUT P36
I/O
output
output
output
output
Function
unspread data
output
data clock
output
PN spread data
output
PN clock output
PN Modulator Registers
The PN modulator is supported by six read/write registers
located in bank (C) of the Expanded Register Group: the
PN modulator control register (PNCON) at %(C)00; the PN
relative address register (PNADDR) at %(C)01; the PN
code length register (PNLEN) at %(C)02; the PN modula-
tor low-byte data hold register (TxBUFL) at %(C)03; the
high-byte data hold register (TxBUFH) at %(C)04; and the
data clock control register (DCLK) at %(C)05. Internally,
the PN modulator also contains the data shift register for
the chips and data bits to be XOR’ed.
PNCON
The PN control register, PNCON, shown in Figure 18 and
located at %(C)00, controls the operation and configura-
tion of the Z87100’s PN modulator. PNCON provides the
following control functions:
D7 D6 D5 D4 D3 D2 D1 D0
PN_ENABLE
0 Disable
1 Enable
REF_CLOCK_SELECT
00 SCLK
01 T0
1X T1
PNCLKOUT_ENABLE
0 P36 I/O
1 P36 PNCLKOUT
PNDOUT_ENABLE
0 P20 I/O
1 P20 DCLKOUT
PNDCLKOUT_ENABLE
0 P27 I/O
1 P27 PNDCLKOUT
PN_MODULATE
0 STOP
1 START
DATA_CLOCK MODE
0 PNLEN-Dependent Data Clock
1 Independent Data Clock
Figure 18. PN Modulator Control Register (PNCON)
PN_ENABLE (PNCON D0) disables or enables the PN
modulator. When disabled (PN_ENABLE=0), clock signals
to the PN modulator circuitry are discontinued, reducing
the overall Z87100 power requirements. When enabled
(PN_ENABLE=1), the PN-spread output PNMODOUT is
automatically directed to P35 of Port 3 and the pins indicat-
ed in Table 4 may, under program control, be selected as
indicated.
Enabling the PN modulator further configures interrupt
IRQ3 to monitor the status of the PN modulator's data shift
register. IRQ3 will initially be cleared (set to 0) but will be
set to 1 after the last bit of the data shift register's contents
has been PN-modulated and the current contents of Tx-
BUFL and TxBUFH have been automatically transferred to
the data shift register. The user then has at most 16 data
bit intervals in which to update TxBUFL and TxBUFH.
IRQ3 may be used to control data input to the PN modula-
tor either as an interrupt or as a polled flag, depending on
whether the EI instruction has been invoked. As an inter-
rupt, IRQ3 will be automatically cleared as the interrupt is
serviced; as a polled flag, IRQ3 must be cleared each time
by manually setting bit 3 of the register to 0.
REF_CLOCK_SELECT (PNCON D1:D2) selects which of
three sources (SCLK, T0, or T1) is used as the PN clock.
PNCLKOUT_ENABLE (PNCON D3) when enabled
(D3=1), selects P36 of Port 3 as the output pin for the PN
modulator’s PN clock. PN_ENABLE must be set.
PNDOUT_ENABLE (PNCON D4), when enabled (D5=1),
selects P20 of Port 2 as the output pin for the unspread
data stream. PN_ENABLE must be set, and P20 must be
configured as an output pin using P20OE of the P2M Port
2 Mode Register.
PNDCLKOUT_ENABLE (PNCON D5), when enabled
(D6=1), selects P27 of Port 2 as the output pin for the un-
spread data’s clock. PN_ENABLE must be set, and P27
must be configured as an output pin using P27OE of the
P2M Port 2 Mode Register.
PN_MODULATE (PNCON D6) turns the PN modulation
function on and off, starting and stopping its operation
once enabled by PN_ENABLE. Setting PN_MODULATE
to 1 from 0 loads the data shift register with the current
contents of the data hold register, TxBUFL and TxBUFH,
and initializes the PN ROM address counter to the start of
the PN sequence according to the value set in PNADDR.
If MODULATE_SELECT is set to 0, the contents of PN
ROM and the data hold register will then be clocked out to
be XOR'ed together; otherwise, if MODULATE_SELECT
is set to 1, only the contents of PN ROM will be clocked
out.
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PRELIMINARY
DS96WRL0700