Z87100 Datasheet, PDF (20/48 Pages) Zilog, Inc. – Wireless Transmitter

Z87100
Wireless Transmitter
FUNCTIONAL DESCRIPTION (Continued)
RC1
R
RC2
RC1
C
R
RC2
RC1
RC2
RC Oscillator
External Clock
Figure 16. RC Oscillator Configuration
Zilog
Ext Clock
RC
Table 4. Maximum Clock Value in Different Modes
Standard Mode
SCLK=RC1/2
12 MHz
(SCLK=6 MHz)
6 MHz
(SCLK = 3 MHz)
Standard Mode
SCLK=RC1
6 MHz
(SCLK = 6 MHz)
3 MHz
(SCLK = 3 MHz)
Low EMI
SCLK= RC1/2
4 MHz
(SCLK = 2 MHz)
1 MHz
(SCLK = 500 kHz)
Low EMI
SCLK=RC1
2 MHz
(SCLK = 2 MHz)
500 kHz
(SCLK = 500 kHz)
Recovery Timer Circuit. A timer circuit clocked by a ded-
icated on-board WDT oscillator or by the RC oscillator or
TMBASE clock oscillator is used as a recovery timer. The
timer allows V_CC and the oscillator circuit to stabilize be-
fore instruction execution begins. The recovery timer cir-
cuit is a one-shot timer triggered by one of the three con-
ditions:
HALT. The HALT instruction turns off the internal CPU
clock but not the selected RC oscillator or TMBASE clock.
The counter/timers and external interrupts IRQ0 and IRQ2
remain active. The device is recovered by interrupts, either
externally or internally generated. After the interrupt, exe-
cution proceeds to the next instruction following the HALT
instruction.
s Power Fail to Power OK status
s Stop-Mode Recovery (If D5 of SMR=1)
s WDT Time-Out
The recovery time is a nominal 5 ms using the internal
WDT oscillator or, if used with the WDT, 256 clock cycles
of the selected externally referenced oscillator. Bit 5 of the
Stop Mode Register determines whether the recovery tim-
er is bypassed after Stop-Mode Recovery.
STOP. This instruction turns off the internal clock and the
RC oscillation and reduces the standby current to 10 µA or
less. The STOP mode is terminated by either WDT time-
out, POR, or SMR recovery. Either of these events causes
the processor to restart the application program at address
000C (HEX). Note that the selected clock source, RC os-
cillator or TMBASE clock, remains active if bits 3 and 4 of
the WDTMR are set. In this mode, only the watch-dog tim-
er runs and the time base generator always remain on.
3-20
PRELIMINARY
DS96WRL0700