Z87100 Datasheet, PDF (28/48 Pages) Zilog, Inc. – Wireless Transmitter

Z87100
Wireless Transmitter
Zilog
FUNCTIONAL DESCRIPTION (Continued)
The time base generator, if mask-optioned, are always on,
but RC is off when not selected. When switching from TM-
BASE to RC, internal circuitry waits for 128 valid clock cy-
cles of TMBASE (4 msec @ 32 kHz) before effecting the
switch from TMBASE to RC to insure that RC has stabi-
lized. Internal circuitry also insures that the switch from RC
to TMBASE or TMBASE to RC is glitch-free. It is recom-
mended that any command to switch oscillators be fol-
lowed by a loop that tests the value of CLOCK_SELECT:
the value of CLOCK_SELECT will only change when the
transition has fully taken place.
MODULATE_SELECT. (TMBASE D4) controls the clock-
ing out of data from the PN modulator's data shift register.
If MODULATE_SELECT is set to 0, the contents of PN
ROM and the data hold register will be clocked out to be
XOR'ed together; otherwise, if MODULATE_SELECT is
set to 1, only the contents of PN ROM will be clocked out.
Timing of this operation depends on whether the data and
PN clocks are integrally related, as determined by
DATA_CLOCK_MODE, and whether PN modulation has
begun, as determined by PN_MODULATE, as shown in
Table 7.
D7 D6 D5 D4 D3 D2 D1 D0
TIMEOUT_SELECT
0 0 0.25 Second
0 1 1.0 Second
1 0 1 Minute
1 1 1 Hour
TIMEOUT_ENABLE
0 Disabled (stop)
1 Enabled (reset and start)
CLOCK_SELECT
0 RC
1 TMBASE
MODULATE_SELECT
0 PN-modulated data
1 PN sequence only
Reserved
Figure 20. Time Base Generator Control Register
PN_MODULATE
0→ 1
MODULATE_SELECT=0
(PN-Modulated Data)
MODULATE_SELECT=1
(PN Sequence Only)
PN_MODULATE=1
MODULATE_SELECT 1→0
(PN Only → PN + Data)
MODULATE_SELECT 0 →1
(PN + Data → PN Only)
Table 7. PN Modulation Stop/Start Control
First data bit and first PN chip of the PN code sequence will be clocked out
together at the next edge of the data clock (dclk).
First PN chip of the PN chip sequence will be clocked out at the next edge
of the data clock (dclk).
If DATA_CLOCK_MODE=0 (integer number of PN code sequences per
bit), then the first data bit will be clocked out with the next repetition of the
first PN chip of the PN code sequence.
If DATA_CLOCK_MODE=1 (independent PN code sequence length and
data bit duration). then the first data bit will be clocked out at the the next
edge of the data clock (dclk) together with the ongoing PN sequence.
Last data bit will be clocked out with the immediately preceding edge of the
data clock (dclk); code sequence output will continue according to the PN
clock (pnclk).
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PRELIMINARY
DS96WRL0700