Z87100 Datasheet, PDF(19/48 Page) Zilog, Inc.

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Z87100 Datasheet, PDF (19/48 Pages) Zilog, Inc. – Wireless Transmitter

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Zilog

Z87100

Wireless Transmitter

Table 2. Interrupt Types, Sources, and Vectors

Name Source

IRQ0 Time Base

IRQ1 IRQ1

IRQ2 IRQ2, TIN

Vector

Location

Comments

0, 1 Internal,

Rising/Falling Edge

Triggered

2, 3 External (P33),

Falling Edge

Triggered

4, 5 External (P31),

Rising/Falling Edge

An interrupt resulting from AN1 (P31) is mapped into IRQ2,

and an interrupt from the time base generator is mapped

3 into IRQ0. Interrupts IRQ2 and IRQ0 may be rising, falling,

or both-edge triggered, and are programmable by the us-

er. The software can poll to identify the state of the pin. For

IRQ0 and the time base generator, selection of the trigger

edge is not critical but should not be changed once select-

ed.

The programming bits for the INTERRUPT EDGE SE-

LECT are located in the IRQ register (R250), bits D7 and

D6. The configuration is shown in Table 3.

Triggered

IRQ3 Software/PN

Modulator

IRQ4 T0

6, 7 Software

Generated/Internal*

8, 9 Internal

IRQ5 TI

10, 11 Internal

Notes:

*When the PN Modulator is enabled, IRQ3 is an internal

interrupt.

Table 3. IRQ0 and IRQ2 Interrupt Edge

Programming

Interrupt

IRQ

Edge Time

Base

When more than one interrupt is pending, priorities are re-

solved by a programmable priority encoder that is con-

trolled by the Interrupt Priority register. An interrupt ma-

chine cycle is activated when an interrupt request is

granted. This disables all subsequent interrupts, saves the

Program Counter and Status Flags, and then branches to

the program memory vector location reserved for that in-

terrupt. All Z87100 interrupts are vectored through loca-

tions in the program memory. This memory location and

the next byte contain the 16-bit starting address of the in-

terrupt service routine for that particular interrupt request.

Notes:

F = Falling Edge

R = Rising Edge

R/F

Clock. The Z87100 derives its timing from an on-board RC

oscillator referenced as RC or an external clock source ap-

plied to the time base counter input referenced as TM-

BASE. The RC clock source is made of an internal oscilla-

tor and an external resistor and an optional external

capacitor (See Figure 14).

To accommodate polled interrupt systems, interrupt inputs

are masked and the interrupt request register is polled to

determine which of the interrupt requests needs services.

When the PN modulator is disabled, IRQ3 has no hard-

ware source but can be invoked by software by setting bit

D3 of the IRQ register to 1. When the PN modulator is en-

abled, an interrupt will be mapped to IRQ3 after the con-

tents of the PN modulator's data hold register have been

loaded into the modulator's data shift register.

The 2 terminals that are part of the RC oscillator are refer-

enced as RC1 and RC2. The frequency of the clock signal

generated by the RC oscillator cannot exceed 6 MHz. RC1

can also be driven by an external clock source, while RC2

remains unconnected. In this configuration the Z87100

can be clocked up to 12 MHz, when not in Low EMI mode.

(4 MHz in Low EMI mode).

Both clock sources, RC and TMBASE, can be selected to

drive the internal Z8 system clock, depending on the set-

ting of a mask-programmed option bit.

The TMBASE clock input requires a 32.768 kHz clock sig-

nal when the TMBASE is enabled or when the TMBASE is

selected to be the default oscillator. As a special feature of

the Z87100, ICC current consumption is significantly re-

duced at a clock frequency of 10 kHz in low EMI noise

mode.

DS96WRL0700

PRELIMINARY

3-19

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