Z87100 Datasheet, PDF (22/48 Pages) Zilog, Inc. – Wireless Transmitter

Z87100
Wireless Transmitter
Zilog
FUNCTIONAL DESCRIPTION (Continued)
While nominal operation assumes that a single PN se-
quence of PNLEN chips corresponds to a single data bit as
described above, the PN modulator additionally supports
modes which allow 2 or 4 bits per PN sequence or 2 or 4
PN sequences per bit or an arbitrary relationship between
the PN and data clocks. The specific relationship between
the selected reference clock, the PN clock, and the data
clock then depends upon the values of the PNLEN and
DCLK registers.
The Z8 loads the data shift register of the PN modulator by
writing to the PN modulator’s 16-bit data hold register, Tx-
BUFL and TxBUFH. As the last bit of the data shift register
is shifted to be XOR’ed, the PN modulator’s control logic
loads the contents of the data hold register into the data
shift register and triggers interrupt IRQ3. Loading of the
next byte of data to TxBUFL and TxBUFH can thus be con-
trolled by Z8 software through interrupts or through polling
by using IRQ3.
MODULATE_SELECT (TMBASE D4) controls whether
the contents of the data hold register are clocked out to be
PN modulated. If MODULATE_SELECT is set to 0, the
contents of PN ROM and the data hold register will then be
clocked out to be XOR'ed together; otherwise, if
MODULATE_SELECT is set to 1, only the contents of PN
ROM will be clocked out.
Typically, one would enable the PN modulator with
PN_ENABLE, select the desired PN code sequence from
PN ROM using PNLEN and PNADDR, configure the de-
sired PN and data clocks using REF_CLOCK_SELECT,
DATA_CLOCK_MODE and DCLK, and select the desired
outputs using PNCLKOUT_ENABLE, PNDOUT_ENABLE
and PNDCLKOUT_ENABLE. With the first data to be
transmitted loaded in the data hold register TxBUFL and
TXBUFH, transmission of PN modulated data or just the
PN code sequence can then begin under control of
PN_MODULATE and MODULATE_SELECT.
Initiation of PN modulation is controlled by three control
bits in the PNCON and TMBASE control registers:
PN_ENABLE,PN_MODULATE,and
MODULATE_SELECT.
PN _ENABLE (PNCON D0) enables the PN modulator by
providing its circuitry with clock signals and configures
IRQ3 and P35 of Port 3.
PN_MODULATE (PNCON D6) initializes the PN ROM ad-
dress counter to the start of the PN sequence, loads the
data shift register with the contents of the data hold regis-
ter, TxBUFH and TxBUFL, and, depending on the value of
MODULATE_SELECT, either begins PN modulation of the
data or begins transmission of the unmodulated PN se-
quence.
PN Modulator I/O. The Z87100 PN modulator outputs and
inputs are multiplexed with the pins of Ports 2 and 3 ac-
cording to Table 4. By enabling the PN modulator with
PN_ENABLE (D0 of PN Modulator Control Register 1,
PNCON1), the PN-modulated data output, PNMODOUT,
is automatically multiplexed to P35. Selection of the other
PN modulator outputs, however, requires explicit enabling
of the associated control bits in PNCON as well as
PN_ENABLE. In that way, as few as one or as many as
four I/O pins may be used in operation of the PN modula-
tor, depending upon the application’s requirements.
3-22
PRELIMINARY
DS96WRL0700