Z87100 Datasheet, PDF (25/48 Pages) Zilog, Inc. – Wireless Transmitter

Zilog
Z87100
Wireless Transmitter
Resetting PN_MODULATE to 0 from 1 stops PN modula- _PNLEN
tion after the current data byte is completely modulated;
i.e., after either the high or low byte of the current contents
of the 16-bit data shift register is completely modulated.
The timing of the command to reset PN_MODULATE must
be monitored by the user, based on the number of cycles
after IRQ3 was last raised, in order to insure that the de-
sired byte is the last byte transmitted.
The PN code length register, PNLEN at %(C)02, indicates
the number of PN chips to be accessed from PN ROM and
modulated against each data bit. If the value of PNLEN
plus PNADDR exceeds FFH, the PN modulator’s control
logic will automatically cycle through PN ROM so that a to-
tal of PNLEN chips are utilized. In some modes, the value
of PNLEN also determines the data rate, where the PN
3
When instructed to stop, the contents of TxBUFL and Tx-
BUFH will not be transferred to the data shift register. Set-
ting PN_MODULATE to 1 will then completely reinitiate PN
modulation beginning with the PN sequence starting at
PNADDR (i.e., the PN sequence will be reset) and with the
modulator’s data shift register is clocked by an integer mul-
tiple or fraction of the selected reference clock divided by
PNLEN. The value of PNLEN must be set prior to starting
operation of the PN modulator; writing to PNLEN while PN
modulation is in process will give indeterminate results.
data word to be modulated as currently stored in the PN
modulator's data hold register, TxBUFL and TxBUFH. In
TxBUFL and TxBUFH
effect, the data shift register contents are flushed when PN The PN modulator’s data hold register, TxBUFL at %(C)03
modulation is stopped.
and TxBUFH at %(C)04, supports the loading of data bytes
by the Z8 core for PN modulation. Data loading may be
DATA_CLOCK_MODE (PNCON D7) controls whether the _{controlled either through software polling or interrupt using}
data and PN clocks are integrally related. When _{IRQ3. The time available to load data depends upon the}
DATA_CLOCK_MODE equals 0, the data and PN clocks _{transmit data rate, itself a function of the speed of the se-}
are integrally related as determined by bits D0, D1, and D2 _{lected reference clock and the value of PNLEN, and, of}
of register DCLK and the value of PNLEN. When _{course, upon the Z87100 clock.}
DATA_CLOCK_MODE equals 1, the PN clock is deter-
mined by the selected reference clock and PNLEN while Note that the data shift register is clocked by the dataclk.
the data clock is independently determined by the refer- Data is shifted for PN modulation D15 first, D0 last in terms
ence clock and DCLK.
of the data loaded into TxBUFL and TxBUFH. The data
shift register, as opposed to TxBUFL and TxBUFH, is not
PNADDR
accessible by the CPU.
The PN relative address register, PNADDR at %(C)01, in-
dicates the starting address within PN ROM to access the
PN sequence to be used in modulation. Addressing is rel-
ative, with PNADDR=00H corresponding to the first PN
chip contained in PN ROM, PNADDR=FFH corresponding
to the last. The value of PNADDR must be set prior to start-
ing operation of the PN modulator; writing to PNADDR
while PN modulation is in process will give indeterminate
results.
DCLK
The data clock control register, DCLK at %(C)05, deter-
mines the relationship within the PN modulator among the
PN clock controlling the PN shift register (pnclk), the data
clock controlling the data shift register (dataclk), and the
selected reference clock (SCLK, or one of the two Z8
counter/timers). A conceptual drawing of the PN modula-
tor’s timing generator is shown in Figure 17, while Table 5
summarizes the following discussion of the various data
clock modes.
When DATA_CLOCK_MODE (PNCON D7) is set to 0, the
first three bits of DCLK (D2, D1, D0) establish an integral
relationship between the data clock and the PN code se-
quence.
DS96WRL0700
PRELIMINARY
3-25