Z87100 Datasheet, PDF (26/48 Pages) Zilog, Inc. – Wireless Transmitter

Z87100
Wireless Transmitter
FUNCTIONAL DESCRIPTION (Continued)
Nominal operation corresponds to DCLK D2=0, D1=0, and
D0=0: the PN clock (pnclk) is then equal to the reference
clock (refclk), and the data clock is equal to refclk divided
by the value of PNLEN. In this way, a complete PN code
sequence as defined by PNLEN corresponds to a single
data bit. The PN modulator output is thus the PN sequence
with its polarity determined by the value of the data bit.
With D2=0, non-zero values of D1 and D0 determine if ref-
clk/PNLEN is further divided by 2D1 D0 to form the data
clock. In other words,
pnclk = refclk,
dataclk = pnclk/(PNLEN x 2D1 D0),
As can be seen, a single data bit may correspond to 2, 4,or
8 PN sequences in this mode.
With D2=1, the PN clock is formed by dividing refclk by 4.
The values of D1 and D0 then determine the relationship
Zilog
of dataclk to refclk and can allow a single PN sequence to
correspond to 2 or 4 data bits:
pnclk = refclk/4,
dataclk = refclk/(PNLEN x 2D1 D0)
or, equivalently,
dataclk = (4/2D1 D0) x pnclk/PNLEN.
When DATA_CLOCK_MODE (PNCON D7) is set to 1, the
number of complete PN code sequences per data bit or
number of data bits per single PN code sequence is not
necessarily an integer. The PN clock is defined by refclk,
while the data clock is determined as refclk/DCLK, using
all 8 bits of DCLK. Although not likely to be used, DCLK =
00H corresponds to a value of 256. The transition edges of
a single chip are still aligned with that of a bit transition, but
the PN code cycle is not necessarily synchronous with
data transitions.
DCLK D2
PNCON D7
(DATA_CLOCK_MODE)
SCLK
T0
Clock
Select
refclk
0
T1
1
÷4
pnclk
(to PN ROM)
DCLK
D1 D0
÷ PNLEN
÷2 ^{D1 D0}
÷ DCLK
0
dataclk
(to DATA SHIFT
REGISTER)
1
PNCON
D7
DATA_CLOCK_MODE
0 dataclk
integrally related
to pnclk
1 independent
dataclk
Figure 19. Conceptual Block Diagram of PN Modulator Timing Generator
3-26
PRELIMINARY
DS96WRL0700