Z87100 Datasheet, PDF (21/48 Pages) Zilog, Inc. – Wireless Transmitter

Zilog
Z87100
Wireless Transmitter
In order to enter STOP (or HALT) mode, it is necessary to The limits of the PN ROM address space are automatically
first flush the instruction pipeline to avoid suspending exe- resolved by the control logic so that the PN ROM is effec-
cution in mid-instruction. To do this, the user executes a
NOP (opcode=FFH) immediately before the appropriate
tively a large circular buffer from which smaller circular
buffers defined by PNLEN and PNADDR can be access-
3
sleep instruction; i.e.,
ed. Operation and control of the circular buffer is transpar-
ent to the user. As long as the sum of code lengths is less
FF
NOP; clear the pipeline
than or equal to 256 chips, more than one PN sequence
6F
STOP; enter STOP mode
or
FF
NOP; clear the pipeline
7F
HALT; enter HALT mode
may be ROM programmed, with the choice of code or even
a concatenation of codes to be used for transmission con-
trolled by Z8 software and the values of PNADDR and PN-
LEN.
Contents of PN ROM are shifted out and XOR’ed with the
PN Modulator. The Z87100 incorporates a PN modulator contents of the data shift register. The rates at which the
to allow generation of a direct sequence spread spectrum two streams are shifted are controlled by the PN and data
data stream. Coupled with the appropriate transmitter cir- clocks so that one or more PN chips are XOR’ed against a
cuitry, the Z87100 can support wireless and power line single data bit, where the number of PN chips is deter-
spread spectrum transmission.
mined by the value of PNLEN. The reference clock for the
The PN modulator of the Z87100 is shown in Figure 15.
Major elements of the PN modulator include the PN ROM,
the PN modulator control logic, the data hold and data
PN modulator may be selected from the internal system
clock (SCLK) or either of the two counter/timers (T0 and
T1).
shift registers, and the clock select multiplexor and PN and In nominal operation, the PN clock is defined by the select-
data clock generator.
ed reference clock, and the data clock is then generated as
As part of the PN modulator, a specially designated area
of ROM (PN ROM) provides space for 256 bits (“chips”) of
one or more pseudorandom noise sequences. The PN
modulator control logic accesses the PN ROM as a circular
buffer and synchronously exclusive-or’s (XORs) each chip
of the sequence with the data bits loaded in the PN modu-
lator's data shift register, thereby PN modulating the data.
The PN code is accessed from the PN ROM beginning at
a specified relative address (PNADDR, register %02 in
bank C of the Expanded Register Group) until the chip cor-
an integer fraction of the PN clock, where the integer is
specified by PNLEN. In this way, each data bit can be syn-
chronously modulated by a full PN code sequence as de-
fined by PNLEN, PNADDR, and the contents of PN ROM.
As a practical matter, this type of symbol-synchronous PN
modulation allows the corresponding spread spectrum re-
ceiver to be designed with improved acquisition perfor-
mance — since the PN and data modulation are synchro-
nously related at the transmitter, PN acquisition at the
receiver can simultaneously establish bit synchronization.
responding to the PN code length (PNLEN, register %03 in
bank C of the Expanded Register Group) is reached, at
which point access continues again from the specified rel-
ative address.
DS96WRL0700
PRELIMINARY
3-21