Z87100 Datasheet, PDF (29/48 Pages) Zilog, Inc. – Wireless Transmitter

Zilog
Z87100
Wireless Transmitter
Table 8. Stop-Mode Recovery Source
SMR (F) 0B
D7 D6 D5 D4 D3 D2 D1 D0
SMR SMR SMR
Operation
D4 D3
D2
Description of Action
3
SCLK/TCLK Divide by 16
0 OFF *
1 ON
0
0
0
0
0
1
0 POR recovery only
1 POR recovery only
0 P31 transition
Clock Divide
0 SCLK = RC1/2*
1 SCLK = RC1
0
1
1
0
1 Time Base Generator
0 P33 transition
Stop-Mode Recovery Source
000 POR Only *
001 POR Only
010 P31
011 Time Base Generator
100 P33
101 P27
110 P2 NOR 0:3
111 P2 NOR 0:7
1
0
1
1
1
1
1 P27 transition
0 Logical NOR of Port 2 bits 0-3
1 Logical NOR of Port 2 bits 0-7
P31 and P33 cannot wake up from STOP mode if the input
lines are configured as analog inputs.
* Default setting after RESET
Stop Delay
0 OFF
1 ON *
Stop Recovery Level
0 Low Level _*
1 High Level
Stop Flag
0 POR _*
1 Stop Recovery
Figure 21. Stop-Mode Register
Stop-Mode Recovery Register (SMR). This register se-
lects the clock divide value and determines the mode of
Stop-Mode Recovery (Figure 19). All bits are write only ex-
cept bit 7, which is read only. Bit 7 is a flag bit that is hard-
ware set on the condition of a STOP recovery and reset on
a power-on cycle. Bit 6 controls whether a low level or high
level is required from the recovery source. Bit 5 controls
the reset delay after recovery. Bits 2, 3, and 4 of the SMR
specify the source of the Stop-Mode Recovery signal. Bit
1 determines whether the selected oscillator, RC or TM-
BASE, is divided by 1 or 2. Bit 0 controls the divide-by-16
prescaler of SCLK/TCLK.
SCLK/TCLK divide-by-16 select (D0). D0 of the SMR
controls a divide-by-16 prescaler of SCLK/TCLK. The pur-
pose of this control is to selectively reduce device power
consumption during normal processor execution (SCLK
control) and/or HALT mode (where TCLK sources the
counter/timers and interrupt logic).
RC1 Clock divide-by-two (D1). This bit determines
whether the RC1 clock is divided by two or one. When this
bit is set to 1, the SCLK/TCLK is equal to the RC1 clock.
This option can work together with the low EMI options in
PCON register to reduce the EMI noise. Maximum clock
frequency is 6 MHz when divide-by-one selection is active.
Stop-Mode Recovery Source (D2,D3,D4). These three
bits of the SMR specify the wake-up source of the Stop-
Mode Recovery (Figure 21 and Table 8).
Stop-Mode Recovery Delay Select (D5). This bit dis-
ables the nominal 5 ms RESET delay provided by the re-
covery timer circuit after Stop-Mode Recovery. The default
condition of this bit is 1, enabling the delay. If this bit is 0,
the extra delay is disabled, limiting the recovery delay to 18
cycles of RC1.
Stop-Mode Recovery Level Select (D6). A 1 in this bit
position indicates that a high level on any one of the recov-
ery sources wakes the device from STOP mode. A 0 indi-
cates low level recovery. The default is 0 on POR (Figure
19).
Cold or Warm Start (D7). This bit is READ only. When the
device enters STOP mode, D7 will be set to 1. D7 will only
be reset to 0 to indicate "cold" start if the device is reset by
either a Power-On Reset or by a Watch-Dog Timer Reset
when the part is in normal operation. Otherwise, if the de-
vice is reset by a Watch-Dog Timer Reset when the part is
in STOP mode or by any other SMR source, then this bit
will continue to be set to 1 to indicate a "warm" start.
Reset Upon Power-On. Upon applying power to the
Z87100, an internal reset pulse is generated which triggers
the timing recovery circuit illustrated in Figure 22. Power-
on reset (POR) behavior is different, however, depending
on whether RC or TMBASE has been selected as the clock
that drives the Z8^®.
When RC is mask-selected to be the Z8 system clock, the
recovery counter is clocked by an internal WDT (Watch-
Dog Timer) oscillator. The system reset initiated by POR
takes 5 ms and guarantees that the RC oscillations are
stabilized before the first instruction is executed by the Z8.
Subsequently, the recovery counter is used as the Watch-
Dog Timer.
When TMBASE is mask-selected to be the default Z8 sys-
tem clock upon power-on, recovery timing is controlled by
the time base generator.
DS96WRL0700
PRELIMINARY
3-29