DS707 Datasheet, PDF (9/20 Pages) Xilinx, Inc – Configurable as single or dual port PS2 controller

LogiCORE IP XPS PS2 Controller (v1.01b)
XPS PS2 Controller Design Parameters
To allow the user to create a XPS PS2 Controller that is uniquely tailored for the user’s system, certain features are
parameterizable in the XPS PS2 Controller design. This allows the user to have a design that utilizes only the
resources required by the system and runs at the best possible performance. The features that are parameterizable
in the XPS PS2 Controller core are as shown in Table 2.
Table 2: XPS PS2 Controller Design Parameters
Generic Feature/Description Parameter Name
Allowable Values
System Parameter
Default
Value
VHDL Type
G1 Target FPGA family C_FAMILY
aspartan3, spartan3,
spartan3a, spartan3e,
spartan3adsp,
virtex4, virtex5,
virtex5fx, aspartan3e,
aspartan3a,
aspartan3adsp,
qvirtex4, qrvirtex4,
spartan6, virtex6,
virtex6cx,spartan6
spartan3
PLB Parameters
string
G2
XPS PS2 Controller
Base Address
C_BASEADDR
Valid Address⁽²⁾
None⁽¹⁾
G3
XPS PS2 Controller
High Address
C_HIGHADDR
Valid Address⁽²⁾
None⁽¹⁾
G4 PLB address width C_SPLB_AWIDTH
32
32
G5 PLB data width
C_SPLB_DWIDTH
32, 64, 128
32
Selects point-to-point
G6 or shared PLB
C_SPLB_P2P
topology
0 = Shared Bus
Topology
0
log₂(C_SPLB_
G7
PLB Master ID Bus
Width
C_SPLB_MID_WIDTH
NUM_MASTERS)
with a minimum value
1
of 1
G8
Number of PLB
Masters
C_SPLB_NUM_
MASTERS
1 - 16
1
G9
Width of the Slave
Data Bus
C_SPLB_NATIVE_
DWIDTH
32
32
G10
Enable burst support
C_SPLB_SUPPORT_
BURSTS
0
0
XPS PS2 Controller Features
std_logic_vector
std_logic_vector
integer
integer
integer
integer
integer
integer
integers
G11 Use dual channel
C_IS_DUAL
0/1
0
integer
G12
PLB Clock Frequency
C_SPLB_CLK_
FREQ_HZ
Valid Frequency⁽³⁾
100000000
integer
1. No default value will be specified to insure that the actual value is set, i.e., if the value is not set, a compiler error will be
generated
2. C_BASEADDR must be a multiple of the range size, where the range size is C_HIGHADDR - C_BASEADDR + 1 and must be
a power of two large enough to accommodate all of the registers
3. Valid Frequency in Hertz, depending on the device family. For spartan3 devices, the frequency can be a maximum of 100MHz.
For virtex4 devices, a maximum of 125MHz and for virtex5 devices, a maximum of 150MHz
DS707 April 19, 2010
www.xilinx.com
9
Product Specification