DS707 Datasheet, PDF (3/20 Pages) Xilinx, Inc – Configurable as single or dual port PS2 controller

LogiCORE IP XPS PS2 Controller (v1.01b)
transmission is inhibited before the 11th clock pulse, the device must abort the current transmission and prepare to
retransmit the current "chunk" of data when host releases clock. A "chunk" of data could be a make code, break
code, device ID, mouse movement packet, etc. For example, if a keyboard is interrupted while sending the second
byte of a two-byte break code, it will need to retransmit both bytes of that break code, not just the one that was
interrupted.
If the host pulls clock low before the first high-to-low clock transition, or after the falling edge of the last clock pulse,
the PS2 device does not need to retransmit any data. However, if new data is created that needs to be transmitted,
it will have to be buffered until the host releases clock.
Figure 1 illustrates the above mentioned device-to-host communication.
X-Ref Target - Figure 1
CLOCK
DATA
START
DATA0
DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 PARITY
STOP
The data line is changed by the device when the clock is low
and is read by the host when the clock is high
Figure 1: Device-to-Host Communication
DS707_01_041910
Host-to-Device Communication
The host-to-device communication happens over 12-bit frames. Since the PS2 device always generates the clock
signal, the host whenever it wants to send data, must inhibit communication by pulling the clock low for at least 100
microseconds. It must then apply a "request-to-send" by pulling data low while releasing the clock signal.
The device should check for this state at intervals not to exceed 10 milliseconds. When the device detects this state,
it will begin generating clock signals and clock in eight data bits and one stop bit. The host changes the data line
only when the clock line is low, and data is read by the device when clock is high. After the stop bit is received, the
device will acknowledge the received byte by bringing the data line low and generating one last clock pulse. If the
host does not release the data line after the 11th clock pulse, the device will continue to generate clock pulses until
the data line is released (the device will then generate an error.)
The host may abort transmission at time before the 11th clock pulse (acknowledge bit) by holding clock low for at
least 100 microseconds.
There are two timings that are needed to be taken care by the state machines. The time it the device to begin
generating clock pulses after the host initially takes the Clock line low, which must be no greater than 15
milliseconds. And the time it takes for the packet to be sent, which must be no greater than 2 milliseconds. If either
of the above time limits is not met, the host should generate an error. If the command sent by the host requires a
DS707 April 19, 2010
www.xilinx.com
3
Product Specification