DS707 Datasheet, PDF (12/20 Pages) Xilinx, Inc – Configurable as single or dual port PS2 controller

LogiCORE IP XPS PS2 Controller (v1.01b)
Table 6 shows the XPS PS2 Port2 interrupt registers and their offset from the base address of XPS PS2 memory map.
Table 6: PS2 Port2 Interrupt Registers
Register Name
Base Address + Offset (hex)
Access
XPS PS2 Port2 Global Interrupt Enable Register (GIE_2)
XPS PS2 Port2 Interrupt Status Register (IPISR_2)
C_BASEADDR + 0x102c
C_BASEADDR + 0x1030
Read/Write
Read/TOW⁽¹⁾
XPS PS2 Port2 Interrupt Enable Register (IPIER_2)
C_BASEADDR + 0x1038
Read/Write
1. TOW = Toggle On Write. Writing a ’1’ to a bit position within the register causes the corresponding bit position in the register to
toggle.
As indicated inTable 6, the interrupt/status/data registers of PS2 Port1 start at the base address and the
interrupt/status/data registers of the PS2 Port2 start at base address + 0x1000.
Depending on whether the parameter C_IS_DUAL is 1 or 0, the status/data registers SRST_2, STATUS_REG2,
RX2_DATA and TX2_DATA and the port2 interrupt registers GIE_2, IPISR_2 and IPIER_2 are included or removed
respectively.
XPS Portx Software Reset Register (SRST_x)
The XPS PS2 Controller has Internal Software Reset Register (SRST_x) for each of its two ports, resetting the
registers independently. The reset register is shown in Figure 4. It is a write only register addressed at an offset 0x0
from base address C_BASEADDR/C_BASEADDR+0x10. The bit definitions of this register are as shown in Table 7.
X-Ref Target - Figure 4
RST
0
31
DS707_04_041910
Figure 4: Software Reset Register (SRST)
Table 7: SRST Register Bit Definitions
Bits
Name
Core
Access
Reset
Value
0 - 31 SRST_x
Write
N/A
Description
Software Reset
A write of 0x0000000A causes reset of the XPS PS2 Controller. A write of
any other value has undefined effect and returns a bus error. A read of this
register returns zero.
XPS PS2 Portx Status Register
The XPS PS2 Portx Status Register indicates the status of the PS2 Portx while transmitting and receiving data
packets. Figure 5 and Table 8 give a more detailed description of the status bits which do the same.
X-Ref Target - Figure 5
Unused
TXx_FULL_STATUS
0
29 30 31
Figure 5: XPS PS2 Status Register
RXx_FULL_STATUS
DS707_05_041910
DS707 April 19, 2010
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Product Specification