DS707 Datasheet, PDF (14/20 Pages) Xilinx, Inc – Configurable as single or dual port PS2 controller

LogiCORE IP XPS PS2 Controller (v1.01b)
Table 10: XPS PS2 Transmit Data Register Description
Bit(s)
Name
Core Access Reset Value
0 to 23
Unused
N/A
0
24 to 31
TXx_DATA
Write
0
Description
Unused
PS2 Portx Transmit Data from the host to device
XPS PS2 Controller Interrupts
The interrupts generated by XPS PS2 Controller are managed by the Interrupt Service Controller (ISC). This unit
provides many of the features commonly provided for interrupt handling.To support interrupt capability for the
two PS2 ports, the PLB interface module implements the following registers:
• Global Interrupt Enable register (GIE)
• IP Interrupt Enable Register (IP IER)
• IP Interrupt Status Register (IP ISR)
The IP IER implements independent interrupt enable bit for each PS2 port while the Global Interrupt Enable
Register provides the master enable/disable for the interrupt output to the processor. The IP ISR implements
independent interrupt status bit for each PS2 port. The IP ISR provides Read and Toggle-On-Write access. The
Toggle-On-Write mechanism for the IP Interrupt Status Register avoids the requirement on the user interrupt
service routine to perform Read-Modify-Write operation to clear the status bit of the interrupt. Read-Modify-Write
operations can lead to inadvertent clearing of interrupts captured in the time period between the read and write
operations. Please refer to the Processor IP Reference Guide under Part 1 for a complete description of the GIE, IPIER
and IPISR.
XPS PS2 Portx Global Interrupt Enable Register (GIE_x)
The Device Global Interrupt Enable Register provides the final enable/disable for the interrupt output to the
processor and resides in the PLB Interface Module. This is a single bit read/write register as shown in Figure 8.
Table 11 shows the GIE bit definitions.
X-Ref Target - Figure 8
Global Interrupt Enable
Unused
01
Figure 8: Device Global Interrupt Enable Register
31
DS707_08_041910
Table 11: Device Global Interrupt Enable Register (GIE) Bit Definitions
Bit(s)
Name
Core
Access
Reset
Value
Description
Master Enable for routing Device Interrupt to the System
Interrupt Controller.
0
Global Interrupt Enable Read/Write
’0’
’1’ = Enabled
’0’ = Disabled
1 to 31
Unused
N/A
0
Unused
DS707 April 19, 2010
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Product Specification