DS707 Datasheet, PDF (5/20 Pages) Xilinx, Inc – Configurable as single or dual port PS2 controller

LogiCORE IP XPS PS2 Controller (v1.01b)
X-Ref Target - Figure 3
XPS PS2 Controller
Internal Registers PS 2
Port 1
PS 2Soft Reset Register
PS2 Port1 SIE
Transmit Data Register
Receiver Data Register
Core Status Register
Transmitter State
Machine
Receiver State
Machine
Watch Dog
Timer
Shift
Registers
Clock
Control
State
Machine
PS2_1_DATA
PS2_1_CLK
Port 1 Interrupt
Service Controller
Global Interrupt
Register
Interrupt Enable
Register
Interrupt Status
Register
6 bits
PLB
Interface
Module
Internal Registers PS2
Port 2
PS2 Soft
Reset Register
Transmit Data
Register
Receive Data
Register
Core Status
Register
PS2 Port 2 SIE
Transmitter
State Machine
Receiver
State Machine
Watch Dog
Timer
Shift
Registers
Clock
Control
State
Machine
PS2_2_DATA
PS2_2_CLK
IP2INTC_Irpt_1
IP2INTC_Irpt_2
Port 2 Interrupt
Service Controller
Global Interrupt
Register
Interrupt Enable
Register
Interrupt Status
Register
6 bits
Figure 3: XPS PS2 Controller Block Diagram
DS707_02_032309
PLB Interface Module
The PLB Interface Module is a bi-directional interface between XPS PS2 Controller IP core and the PLB. To simplify
the process of attaching a XPS PS2 Controller to the PLB, the core makes use of a portable, pre-designed bus
interface called PLB Interface Module, that takes care of the bus interface signals, bus protocols and other interface
issues. The base element of the PLB Interface Module is slave attachment, which provides the basic functionality of
PLB slave operation.
DS707 April 19, 2010
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Product Specification