DS707 Datasheet, PDF (8/20 Pages) Xilinx, Inc – Configurable as single or dual port PS2 controller

LogiCORE IP XPS PS2 Controller (v1.01b)
Table 1: XPS PS2 Controller I/O Signal Description (Cont’d)
Port
Signal Name
Interface I/O
Initial
State
Description
P28 Sl_SSize[0:1]
PLB
O
0
Slave data bus size
P29 Sl_wait
PLB
O
0
Slave wait
P30 Sl_rearbitrate
PLB
O
0
Slave bus rearbitrate
P31 Sl_wrDAck
PLB
O
0
Slave write data acknowledge
P32 Sl_wrComp
PLB
O
0
Slave write transfer complete
P33 Sl_rdDBus[0: C_SPLB_DWIDTH - 1]
PLB
O
0
Slave read data bus
P34 Sl_rdDAck
PLB
O
0
Slave read data acknowledge
P35 Sl_rdComp
PLB
O
0
Slave read transfer complete
P36
Sl_MBusy[0:C_SPLB_NUM_
MASTERS - 1]
PLB
O
0
Slave busy
P37
Sl_MWrErr[0:C_SPLB_NUM_
MASTERS - 1]
PLB
O
0
Slave write error
P38
Sl_MRdErr[0:C_SPLB_NUM_
MASTERS - 1]
PLB
O
0
Slave read error
Unused PLB Slave Interface Output Signals
P39 Sl_wrBTerm
PLB
O
0
Slave terminate write burst transfer
P40 Sl_rdWdAddr[0:3]
PLB
O
0
Slave read word address
P41 Sl_rdBTerm
PLB
O
0
Slave terminate read burst transfer
P42
Sl_MIRQ[0: C_SPLB_NUM_
MASTERS - 1]
PLB
O
0
Master interrupt request
XPS PS2 Controller Signals
P43 PS2_1_DATA
PS2
I/O
Z
Bi-directional Port1 Data
P44 PS2_1_CLK
PS2
I/O
Z
Bi-directional Port1 Clock
P45 PS2_2_DATA
PS2
I/O
Z
Bi-directional Port2 Data
P46 PS2_2_CLK
PS2
I/O
Z
Bi-directional Port2 Clock
P47 IP2INTC_Irpt_1
PS2
O
0
Active High Level Triggered Interrupt
Signal from Port1
P48 IP2INTC_Irpt_2
PS2
O
0
Active High Level Triggered Interrupt
Signal from Port2
DS707 April 19, 2010
www.xilinx.com
8
Product Specification