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DS707 Datasheet, PDF (10/20 Pages) Xilinx, Inc – Configurable as single or dual port PS2 controller
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LogiCORE IP XPS PS2 Controller (v1.01b)
Allowable Parameter Combinations
The address-range size specified by C_BASEADDR and C_HIGHADDR must be a power of 2, and must be at least
0x40 in the single port mode. The address range should be at least 0x1040 in the dual port mode, so that the registers
associated with the second port are also accommodated.
For example, if C_BASEADDR = 0xE0000000, C_HIGHADDR must be at least = 0xE000003F, when C_IS_DUAL =
0. The address range size when C_IS_DUAL = 0 is (0xE000003F - 0xE0000000) + 1 = 0x40. And C_HIGHADDR must
be at least = 0xE000103F, when C_IS_DUAL = 1. The address range when C_IS_DUAL = 1 is (0xE000103F -
0xE0000000) + 1 = 0x1040.
XPS PS2 Controller Parameter - Port Dependencies
The dependencies between the XPS PS2 Controller core design parameters and I/O signals are described in Table 3.
In addition, when certain features are parameterized out of the design, the related logic will no longer be a part of
the design. The unused input signals and related output signals are set to a specified value.
Table 3: XPS PS2 Controller Design Parameter - Port Dependencies
Generic or
Port
Name
Affects
Depends
Relationship Description
Design Parameters
G4
C_SPLB_AWIDTH
G5
C_SPLB_DWIDTH
G7
C_SPLB_MID_WIDTH
G8
C_SPLB_NUM_MASTERS
G11
C_IS_DUAL
P3
P7,P10,
P33
P5
P36,P37,
P38,P42
P45,P46,
P48
I/O Signals
-
Affects number of bits in address
bus
-
Affects number of bits in data bus
Affects the width of current master
G8
identifier signals and depends on
log2(C_SPLB_NUM_MASTERS)
with a minimum value of 1
-
Affects the width of busy and error
signals.
When C_IS _DUAL is 1, port2 is
created
P3
PLB_ABus[0: C_SPLB_AWIDTH - 1]
-
P5
PLB_masterID[0:
C_SPLB_MID_WIDTH- 1]
-
P7
PLB_BE[0: (C_SPLB_DWIDTH/8)-1]
-
P10
PLB_wrDBus[0: C_SPLB_DWIDTH - 1]
-
P32
Sl_rdDBus[0: C_SPLB_DWIDTH - 1]
-
P36
Sl_MBusy[0: C_SPLB_NUM_
MASTERS - 1]
-
P37
Sl_MWrErr[0: C_SPLB_NUM_
MASTERS - 1]
-
G4
Width varies with the size of the PLB
address bus
G7
Width varies with the size of the PLB
master identifier bus
G5
Width varies with the size of the PLB
data bus
G5
Width varies with the size of the PLB
data bus
G5
Width varies with the size of the PLB
data bus
G8
Width varies with the size of the PLB
number of masters
G8
Width varies with the size of the PLB
number of masters
DS707 April 19, 2010
www.xilinx.com
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Product Specification
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