DS707 Datasheet, PDF (7/20 Pages) Xilinx, Inc – Configurable as single or dual port PS2 controller

LogiCORE IP XPS PS2 Controller (v1.01b)
XPS PS2 Controller I/O Signals
The XPS PS2 Controller I/O signals are listed and described in Table 1. All signals are active high.
Table 1: XPS PS2 Controller I/O Signal Description
Port
Signal Name
Interface I/O
Initial
State
Description
System Signals
P1 SPLB_Clk
P2 SPLB_Rst
System
I
System
I
-
PLB clock
-
PLB reset
PLB Slave Interface Input Signals
P3 PLB_ABus[0: C_SPLB_AWIDTH - 1]
PLB
I
P4 PLB_PAValid
PLB
I
P5
PLB_masterID[0:
C_SPLB_MID_WIDTH - 1]
PLB
I
P6 PLB_RNW
PLB
I
P7 PLB_BE[0: (C_SPLB_DWIDTH/8) - 1]
PLB
I
P8 PLB_size[0:3]
PLB
I
P9 PLB_type[0:2]
PLB
I
P10 PLB_wrDBus[0: C_SPLB_DWIDTH - 1]
PLB
I
-
PLB address bus
-
PLB primary address valid
-
PLB current master identifier
-
PLB read not write
-
PLB byte enables
-
PLB size of requested transfer
-
PLB transfer type
-
PLB write data bus
Unused PLB Slave Interface Input Signals
P11 PLB_UABus[0: 31]
P12 PLB_SAValid
P13 PLB_rdPrim
P14 PLB_wrPrim
P15 PLB_abort
P16 PLB_busLock
P17 PLB_MSize
P18 PLB_lockErr
P19 PLB_wrBurst
P20 PLB_rdBurst
P21 PLB_wrPendReq
P22 PLB_rdPendReq
P23 PLB_wrPendPri[0:1]
P24 PLB_rdPendPri[0:1]
P25 PLB_reqPri[0:1]
P26 PLB_TAttribute[0:15]
PLB
I
PLB
I
PLB
I
PLB
I
PLB
I
PLB
I
PLB
I
PLB
I
PLB
I
PLB
I
PLB
I
PLB
I
PLB
I
PLB
I
PLB
I
PLB
I
-
PLB upper address bits
-
PLB secondary address valid
-
PLB secondary to primary read request
indicator
-
PLB secondary to primary write
request indicator
-
PLB abort bus request
-
PLB bus lock
-
PLB data bus width indicator
-
PLB lock error
-
PLB burst write transfer
-
PLB burst read transfer
-
PLB pending bus write request
-
PLB pending bus read request
-
PLB pending write request priority
-
PLB pending read request priority
-
PLB current request priority
-
PLB transfer attribute
PLB Slave Interface Output Signals
P27 Sl_addrAck
PLB
O
0
Slave address acknowledge
DS707 April 19, 2010
www.xilinx.com
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Product Specification