DS707 Datasheet, PDF (6/20 Pages) Xilinx, Inc – Configurable as single or dual port PS2 controller

LogiCORE IP XPS PS2 Controller (v1.01b)
Interrupt Service Controller
The Interrupt Service Controller is a continuation of the Xilinx family of IBM CoreConnect compatible LogiCORE
products. It provides interrupt capture support for the connected IP function. The interrupts from XPS PS2
Controller are connected to the Interrupt Service Controller and the corresponding bits in the Interrupt Status
Register get updated. Interrupt Service Controller provides following functions:
• Parameterized number of interrupts needed by the IP.
• Provides both Interrupt Status Register (ISR) and Interrupt Enable Register (IER) functions for the user IP.
Depending on which interrupt bits are enabled in the IER, the corresponding interrupts from the IP would be
or-ed and a single interrupt would be generated.
Serial Interface Engine
The Serial Interface Engine has the following modules:
• Transmit State Machine - There are 2 separate transmit state machines for each of the PS2 ports. This helps each
of the ports to transmit simultaneously irrespective of the other port. The transmit state machine serializes the
data written into the transmit data register and sends it over the data line as per the PS2 protocol as mentioned
above in the Host-to-Device Communication section.
• Receive State Machine - There are 2 separate receive state machines for each of the PS2 ports. This helps each of
the ports to receive simultaneously irrespective of the other port. The receive state machine does the
serial-to-parallel conversion of the serial data received on the data line and writes into the receive data register
and sends it over the data line as per the PS2 protocol as mentioned above in the Device-to-Host
Communication section.
• Shift Registers - The parallel-to-serial and serial-to-parallel conversion of data by the transmit state machines
and receive state machine respectively, is done by using these shift registers.
• Clock Control State Machine - This state machine detects the rise and fall of the clock line. This edge detection
is required for the transmit and receive state machines to perform the operation. The PS2 protocol is greatly
dependent on the edge of the clock.
• Watch Dog Timer- The watch dog timer keeps a watch on the clock line while transmitting. If the clock line
goes into the pull-up mode in between transmission, the watch dog timer sets the corresponding interrupt. If
there are no transitions on the clock for 200 microseconds, the watch timer would set the interrupt.
Internal Registers
The XPS PS2 controller has eight internal registers, four registers for each of the PS2 ports. The whole operation
happens through the internal registers. For transmitting data to the PS2 device, the data needs to be written into the
transmit register and similarly the receive register would get updated as soon as the data is received from the PS2
device. A more detailed description of these registers is given in the XPS PS2 Controller Register Descriptions
section.
DS707 April 19, 2010
www.xilinx.com
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Product Specification