DS707 Datasheet, PDF (11/20 Pages) Xilinx, Inc – Configurable as single or dual port PS2 controller

LogiCORE IP XPS PS2 Controller (v1.01b)
Table 3: XPS PS2 Controller Design Parameter - Port Dependencies (Cont’d)
Generic or
Port
Name
Affects
Depends
Relationship Description
P38
Sl_MRdErr[0: C_SPLB_NUM_
MASTERS - 1]
-
G8
Width varies with the size of the PLB
number of masters
P42
Sl_MIRQ[0: C_SPLB_NUM_
MASTERS - 1]
-
G8
Width varies with the size of the PLB
number of masters
P45
PS2_2_DATA
-
G11
Depends on whether the dual
channel is enabled
P46
PS2_2_CLK
-
G11
Depends on whether the dual
channel is enabled
XPS PS2 Controller Register Descriptions
There are eight internal registers in the XPS PS2 Controller design as shown in Table 4. These registers are
implemented in the PS2_REG interface module. The memory map of the XPS PS2 Controller design is determined
by setting the C_BASEADDR parameter. The internal registers of the XPS PS2 Controller are at a fixed offset from
the base address. The XPS PS2 Controller internal registers and their offset are listed in Table 4.
Table 4: XPS PS2 Controller Internal Registers
Register Name
Description
Base Address + Offset (hex)
Access
SRST_1
XPS PS2 Port1 Software Reset Register
C_BASEADDR + 0x0000
Write
STATUS_REG1
XPS PS2 Port1 Status Register
C_BASEADDR + 0x0004
Read
RX1_DATA
XPS PS2 Port1 Receive Data Register
C_BASEADDR + 0x0008
Read
TX1_DATA
XPS PS2 Port1 Transmit Data Register
C_BASEADDR + 0x000C
Write
SRST_2
XPS PS2 Port2 Software Reset Register
C_BASEADDR + 0x1000
Write
STATUS_REG2
XPS PS2 Port2 Status Register
C_BASEADDR + 0x1004
Read
RX2_DATA
XPS PS2 Port2 Receive Data Register
C_BASEADDR + 0x1008
Read
TX2_DATA
XPS PS2 Port2 Transmit Data Register
C_BASEADDR + 0x100C
Write
1. Writing into a read-only register or reading a write-only register would generate an error. This would be communicated to the PLB
Interface Module. Such a transaction would not be a valid transaction.
2. The default value of all the above mentioned registers is zeros.
Table 5 shows the XPS PS2 Port1 interrupt registers and their offset from the base address of XPS PS2 memory map.
Table 5: PS2 Port1 Interrupt Registers
Register Name
Base Address + Offset (hex)
Access
XPS PS2 Port1 Global Interrupt Enable Register (GIE_1)
XPS PS2 Port1 Interrupt Status Register (IPISR_1)
C_BASEADDR + 0x002c
C_BASEADDR + 0x0030
Read/Write
Read/TOW⁽¹⁾
XPS PS2 Port1 Interrupt Enable Register (IPIER_1)
C_BASEADDR + 0x0038
Read/Write
1. TOW = Toggle On Write. Writing a ’1’ to a bit position within the register causes the corresponding bit position in the register to
toggle.
DS707 April 19, 2010
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Product Specification