DS707 Datasheet, PDF (16/20 Pages) Xilinx, Inc – Configurable as single or dual port PS2 controller

LogiCORE IP XPS PS2 Controller (v1.01b)
Table 13: XPS PS2 Portx Interrupt Enable Register (IPIER) Bit Definitions
Bit(s)
Name
Core Access
Reset
Value
Description
Enable/Disable Portx RX Data Register Overflow Interrupt
28
RXx_OVF
Read/Write
’0’ ’1’ = Enabled
’0’ = Disabled (masked)
Enable/Disable Portx TX Data Acknowledge Received
Interrupt
29
TXx_ACKF
Read/Write
’0’
’1’ = Enabled
’0’ = Disabled (masked)
Enable/Disable Portx TX Data Acknowledge not Received
Interrupt
30
TXx_NOACK
Read/Write
’0’
’1’ = Enabled
’0’ = Disabled (masked)
Enable/Disable Portx Watch Dog Timer Timeout Interrupt
31
WDTx_TOUT
Read/Write
’0’ ’1’ = Enabled
’0’ = Disabled (masked)
Design Implementation
Target Technology
The target technology is an FPGA listed in the Supported Device Family field of the LogiCORE Facts table.
Device Utilization and Performance Benchmarks
Core Performance
Because the XPS PS2 Controller core will be used with other design modules in the FPGA, the utilization and timing
numbers reported in this section are estimates only. When the XPS PS2 Controller core is combined with other
designs in the system, the utilization of FPGA resources and timing of the XPS PS2 Controller design will vary from
the results reported here.
The XPS PS2 Controller resource utilization for various parameter combinations measured with the Virtex-4 FPGA
as the target device are detailed in Table 14.
Table 14: Performance and Resource Utilization Benchmarks for a Virtex-4 FPGA (xc4vfx60-10-ff672)
Parameter Values
Device Resources
Performance
C_IS_DUAL
Slices
Slice
Flip-Flops
LUTs
F_MAX (MHz)
0
451
367
465
129
1
785
616
844
132
DS707 April 19, 2010
www.xilinx.com
16
Product Specification