DS707 Datasheet, PDF (19/20 Pages) Xilinx, Inc – Configurable as single or dual port PS2 controller

X-Ref Target - Figure 13
X-Ref Target - Figure 14
LogiCORE IP XPS PS2 Controller (v1.01b)
XCL
XCL
MPMC
XPS CDMA
XPS CDMA
Device Under
Test (DUT)
MicroBlaze
Processor
PLBV46
XPS BRAM
XPS INTC
XPS GPIO
XPS UART
Lite
MDM
DS707_13_041910
Figure 13: Virtex-6 FPGA System with the XPS PS2 Controller as the DUT
MPMC
XPS CDMA
XPS CDMA
Device Under
Test (DUT)
MicroBlaze
Processor
PLBV46
XPS BRAM
XPS INTC
XPS GPIO
XPS UART
Lite
MDM
DS707_14_041910
Figure 14: Spartan-6 FPGA System with the XPS PS2 Controller as the DUT
The target FPGA was then filled with logic to drive the LUT and BRAM utilization to approximately 70% and the
I/O utilization to approximately 80%. Using the default tool options and the slowest speed grade for the target
FPGA, the resulting target F_MAX numbers are shown in Table 19.
Table 19: XPS PS2 Controller Core System Performance
Target FPGA
S3A700 -4
Target F_MAX (MHz)
90
V4FX60 -10
100
V5LX50t -1
125
S6LX45t -2
100
V6LX130t -1
150
The target F_MAX is influenced by the exact system and is provided for guidance. It is not a guaranteed value across
all systems.
Specification Exceptions
N/A
DS707 April 19, 2010
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19
Product Specification