DS707 Datasheet, PDF (2/20 Pages) Xilinx, Inc – Configurable as single or dual port PS2 controller

LogiCORE IP XPS PS2 Controller (v1.01b)
Functional Description
The XPS PS2 Controller is a slave IP core designed to control two PS2 devices such as a keyboard and a mouse. To
control the two PS2 devices, it uses simple state machines and shift registers. Each of the PS2 ports is controlled by
a separate set of four byte-wide registers. For transmitting data, a byte is written to the transmit register and then
the Serial Interface Engine serializes the data and transmits to the PS2 device. Transmit status registers and
interrupts indicate whether the transmission is complete and if there are any errors reported. While receiving data,
the Serial Interface Engine receives serial data from the PS2 device and writes into the receive register. Similar to the
transmit status registers, receive status registers and interrupts indicate whether data has been received from the
PS2 device. Any errors in the received data are also reported. The XPS PS2 Controller generates interrupts upon
various transmit and receive conditions.The XPS PS2 Controller can be operated in a polled mode or an interrupt
driven mode.
PS2 Communication
The PS2 protocol consists of host-to-device and device-to-host communication. In the description below "host"
implies the XPS PS2 Controller and "device" implies any PS2 device, which would be a keyboard or a mouse.
The PS2 protocol is a bidirectional synchronous serial protocol. The data and the clock are the two signals through
which communication between the device and the host happens. The host is given the ultimate control of the data
bus. The basic states which can be defined based on the status of the data and clock lines are:
• Idle State - Data is high and clock is high. This is the only state where the PS2 device is allowed to start
transmission of data (during device-to-host communication).
• Communication Inhibited State - Data high and clock low. The device always generates the clock signal. But
since the host has the ultimate control of the bus and may inhibit communication anytime, it must pull the
clock signal low and inhibit the transmission by the device and then initiate transmission from its side.
• Host Request-to-Send State - Data is low and clock is high. The host after inhibiting the communication, will
pull the data line low and release the clock inline, signalling the device that host would transmit data.
All the data is transmitted one byte at a time and each byte is sent in a frame consisting of 11-12 bits (depending on
whether it is host-to-device or device-to-host communication). These bits are:
• 1 start bit. This is always 0
• 8 data bits, least significant bit first
• 1 parity bit (odd parity)
• 1 stop bit. This is always 1
• 1 acknowledge bit (host-to-device communication only)
The data sent from the device to host is read on the falling edge and the data sent from the host to device is read on
the rising edge. The clock frequency must be in the range 10-16.7 kHz. This means clock must be high for 30 - 50
microseconds and low for 30 - 50 microseconds. The keyboard, mouse or host emulator should modify/sample the
data line in the middle of each cell, i.e. 15 - 25 microseconds after the appropriate clock transition.
Device-to-Host Communication
The device-to-host communication happens over 11-bit frames. When the keyboard or mouse wants to send
information, it first checks the clock line to make sure it's at a high logic level. If it's not, the host is inhibiting
communication and the device must buffer any to-be-sent data until the host releases clock. The clock line must be
continuously high for at least 50 microseconds before the device can begin to transmit data.
The host may inhibit communication at any time by pulling the clock line low for at least 100 microseconds. If a
DS707 April 19, 2010
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Product Specification