DS587 Datasheet, PDF (9/20 Pages) Xilinx, Inc – Selectable ADC resolution

XPS Delta-Sigma Analog to Digital Converter (ADC) (v1.01a)
Allowable Parameter Combinations
The address-range size specified by C_BASEADDR and C_HIGHADDR must be a power of 2, and
must be at least 0x200.
For example, if C_BASEADDR = 0xE0000000, C_HIGHADDR must be at least = 0xE00001FF.
XPS ADC Parameter - Port Dependencies
The dependencies between the XPS ADC core design parameters and I/O signals are described in
Table 5. In addition, when certain features are parameterized out of the design, the related logic will no
longer be a part of the design. The unused input signals and related output signals are set to a specified
value.
Table 5: XPS ADC Design Parameter - Port Dependencies
Generic or
Port
Name
Affects Depends
Design Parameters
G4
C_SPLB_AWIDTH
P4
-
G5
C_SPLB_DWIDTH
P8,P11,
P34
-
G7
C_SPLB_MID_WIDTH
P6
G8
G8
C_SPLB_NUM_
MASTERS
P37,P38,
P39,P43
-
I/O Signals
P4
PLB_ABus[0:
C_SPLB_AWIDTH - 1]
-
G4
PLB_masterID[0:
P6
C_SPLB_MID_WIDTH -
-
G7
1]
PLB_BE[0:
P8
(C_SPLB_DWIDTH/8)
-
G5
-1]
P11
PLB_wrDBus[0:
C_SPLB_DWIDTH - 1]
-
G5
P34
Sl_rdDBus[0:
C_SPLB_DWIDTH - 1]
-
G5
Sl_MBusy[0:
P37
C_SPLB_NUM_
MASTERS - 1]
-
G8
Relationship Description
Affects number of bits in address bus.
Affects number of bits in data bus.
Affects the width of current master
identifier signals and depends on
log₂(C_SPLB_NUM_MASTERS) with a
minimum value of 1.
Affects the width of busy and error
signals.
Width varies with the size of the PLB
address bus.
Width varies with the size of the PLB
master identifier bus.
Width varies with the size of the PLB
data bus.
Width varies with the size of the PLB
data bus.
Width varies with the size of the PLB
data bus.
Width varies with the size of the PLB
number of masters.
DS587 December 2, 2009
www.xilinx.com
9
Product Specification