DS587 Datasheet, PDF (4/20 Pages) Xilinx, Inc – Selectable ADC resolution

XPS Delta-Sigma Analog to Digital Converter (ADC) (v1.01a)
Table 1: Delta-Sigma DAC Interface Signals
Signal Direction
Description
Clk
Input Positive edge clock for the Sigma Latch and the DACout flip-flop.
Rst
Input Reset initializes the Sigma Latch and the DACout flip-flop. In this implementation,
Sigma Latch is initialized to a value that corresponds to DACin of 0. If DACin starts
at zero, there is no discontinuity.
DACin
Input
Digital input bus. Value must be stable at the positive edge of Clk. For high-speed
operation, DACin should be sourced from a pipeline register that is clocked with Clk.
For full resolution, each DACin value must be averaged over 2^{(C_DACIN_WIDTH)}
clocks, so DACin should change only on intervals of 2^{(C_DACIN_WIDTH)} clock cycles.
DACout
Output Pulse string that drives the external low pass filter (via an output driver such as
OBUF_F_24).
The Analog to Digital Converter uses an external analog comparator which compares the input voltage
to a voltage generated by the DAC. Figure 3 shows how a typical implementation of analog to digital
conversion is performed using the XPS ADC. A Delta-Sigma DAC, which is a primary block of the XPS
ADC core, is used to generate a reference voltage ADCref for the negative input to the external
comparator.
The analog signal, AnalogIn, feeds the positive input of the comparator. The voltage range of the Delta-
Sigma DAC output is 0V to V_CCO, where V_CCO is the supply voltage applied to the FPGA I/O bank.
This is also the range of analog voltage that can be converted.
If the analog input voltage is outside the range 0 V to V_CCO, either the Delta-Sigma DAC output or the
analog signal itself may be biased, attenuated or amplified with external components to achieve the
desired voltage range compatibility.
The analog voltage level is determined by performing a serial binary voltage search, starting at the
middle of the voltage range.
Because of the serial nature of both the Delta-Sigma DAC and the analog sampling process, this XPS
ADC is useful only on signals that change slowly. If the analog input voltage changes during the
sampling process, it effectively causes the sample point to move randomly. This adds a noise
component that becomes larger as the input frequency increases. This noise component can be
removed with an external sample and hold circuit for the analog input signal.
A 24 mA LVTTL output buffer is normally used to drive the RC filter. Most comparators have
uncommitted collector/drain outputs, so R_P is usually needed.
X-Ref Target - Figure 3
Vcco
FPGA
AnalogIn
RP
–
+
AgtR
OBUF_F_24
R
DACout
C
Comparator
XPS ADC
PLB
Sample
DS587_03_090809
Figure 3: Implementation of Analog to Digital Converter Using XPS ADC
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DS587 December 2, 2009
Product Specification